Moteur de recherche de fiches techniques de composants électroniques |
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ST162552 Fiches technique(PDF) 6 Page - Exar Corporation |
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ST162552 Fiches technique(HTML) 6 Page - Exar Corporation |
6 / 28 page 3-140 ST16C2552 ST16C2552 ACCESSIBLE REGISTERS A/B A2 A1 A0 Register BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 0 0 0 RHR bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 0 THR bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 IER 0 0 0 0 modem receive transmit receive status line holding holding interrupt status register register interrupt 0 1 0 FCR RCVR RCVR 0 0 DMA XMIT RCVR FIFO trigger trigger mode FIFO FIFO enable MSB) (LSB) select reset reset 0 1 0 ISR 0/ 0/ 0 0 int int int int FIFOs FIFOs priority priority priority status enabled enabled bit-2 bit-1 bit-0 0 1 1 LCR divisor set set even parity stop word word latch break parity parity enable bits length length enable bit-1 bit-0 1 0 0 MCR 0 0 0 loop OP2* OP1* RTS* DTR* back 1 0 1 LSR 0/ trans. trans. break framing parity overrun receive FIFO empty holding interrupt error error error data error empty ready 1 1 0 MSR CD RI DSR CTS delta delta delta delta CD* RI* DSR* CTS* 1 1 1 SPR bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 0 DLL bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 DLM bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 0 1 0 AFR 000 00 MF* MF* SP sel-1 sel-0 write These registers are accessible only when LCR bit-7 is set to “1”. |
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