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NTE1639 Datasheet(Fiches technique) 3 Page - NTE Electronics

Numéro de pièce NTE1639
Description  Integrated Circuit CMOS Clock Generator/Driver for BBDs
Télécharger  4 Pages
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Fabricant  NTE [NTE Electronics]
Site Internet  http://www.nteinc.com
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 3 page
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Pin Descriptions:
Pin No.
Symbol
Pin Name
Description
1
GND
Ground
Connected to GND of the circuit.
2
CP1
Clock Output 1
This pin outputs a clock signal that is the reverse
phase of CP2 with a Duty Cycle of 1/2 the frequency
of oscillation.
3
VDD
VDD apply
–15V is applied
4
CP2
Clock Output 2
This pin outputs a clock signal that is a the reverse
phase of CP1
5
OX3
OSC connections to
R, C are connected for the In case of separate excita-
6
OX2
C1, R2, and R1
separately
internal clock.
tion, OX3 and OX2 are
opened and OX1 is set to
7
OX1
separately
opened and OX1 is set to
OSC input.
8
VGG OUT
VGG Voltage Output –14V is output. (VDD = –15V) VGG OUT = 14/15VDD.
The Maximum Clock Frequency:
The upper limit value of the clock frequency is determined by the load capacitance and power con-
sumption. The maximum power dissipation for the NTE1639 is PD = 200mW. If the clock frequency
of the load capacitance is increased, the power consumption will be increased. Accordingly, in order
to utilize this device with a dissipation less than the permissible value, it is necessary to select ade-
quate values for the clock frequency and load capacitance. By connecting a resistance to the clock
output pin, it is possible to increase the value of the maximum clock frequency without increasing dis-
sipation. Because the dissipation on the LSI side is lessened, part of the power consumption required
for driving the load capacitance is consumed by the series resistance.
Pin Connection Diagram
VGG (Out)
VDD
1
2
3
4
GND
CP 1
CP 2
8
7
6
5
OX 1
OX 2
OX 3




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