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TPD2E001DRST-NM Fiches technique(PDF) 8 Page - Texas Instruments

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No de pièce TPD2E001DRST-NM
Description  Low-Capacitance 2-Channel ESD-Protection for High-Speed Data Interfaces
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
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TPD2E001DRST-NM Fiches technique(HTML) 8 Page - Texas Instruments

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VCC
GND
= VIA to GND
IO2
IO1
8
TPD2E001
SLLS684I – JULY 2006 – REVISED MARCH 2016
www.ti.com
Product Folder Links: TPD2E001
Submit Documentation Feedback
Copyright © 2006–2016, Texas Instruments Incorporated
bypass.
2. If the VCC pin is not connected to the system power supply, the TPD2E001 can tolerate higher signal swing
in the range up to 10 V. Please note that a 0.1-
μF capacitor is still recommended at the VCC pin for ESD
bypass.
8.2.2.1 Signal Range on IO1 and IO2 and VCC Pins
The TPD2E001 has 2 IO pins which support 0 to either 10 V or VCC + Vforward (depending on if the VCC pin is
connected to a VCC line or has a 0.1 µF capacitor to ground).
9 Power Supply Recommendations
This device is a passive ESD protection device and there is no need to power it. Care should be taken to make
sure that the maximum voltage specifications for each line are not violated.
10 Layout
10.1 Layout Guidelines
The optimum placement is as close to the connector as possible.
EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Example
This application is typical of a differential data pair application, such a USB 2.0.
Figure 6. Routing With DRL Package


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