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GS8128032GT-333I Fiches technique(PDF) 5 Page - GSI Technology |
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GS8128032GT-333I Fiches technique(HTML) 5 Page - GSI Technology |
5 / 24 page TQFP Pin Description Symbol Type Description A0, A1 I Address field LSBs and Address Counter preset Inputs A I Address Inputs DQA DQB DQC DQD I/O Data Input and Output pins NC No Connect BW I Byte Write—Writes all enabled bytes; active low BA, BB I Byte Write Enable for DQA, DQB Data I/Os; active low BC, BD I Byte Write Enable for DQC, DQD Data I/Os; active low CK I Clock Input Signal; active high GW I Global Write Enable—Writes all bytes; active low E1, E3 I Chip Enable; active low G I Output Enable; active low ADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep Mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active low VDD I Core power supply VSS I I/O and Core Ground VDDQ I Output driver power supply NC — No Connect NU — Not Used—There is an internal chip connection to these pins, but they are unused by the device. They may be left unconnected, tied Low (to VSS), or tied High (to VDDQ or VDD). GS8128018/32/36GT-400/333/250/200 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.01 5/2017 5/23 © 2015, GSI Technology |
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