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GS82582Q36GE-357 Fiches technique(PDF) 10 Page - GSI Technology

No de pièce GS82582Q36GE-357
Description  288Mb SigmaQuad-IITM Burst of 2 SRAM
Download  32 Pages
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Fabricant  GSI [GSI Technology]
Site Internet  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS82582Q36GE-357 Fiches technique(HTML) 10 Page - GSI Technology

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GS82582Q18/36GE-357/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2016
10/31
© 2012, GSI Technology
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 175
 and 350. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps.
Power-Up Initialization
After power-up, stable input clocks must be applied to the device for 20
s prior to issuing read and write commands. See the tKInit
timing parameter in the AC Electrical Characteristics section.
Note:
The tKInit requirement is independent of the tLock requirement, which specifies how many cycles of stable input clocks (2048)
must be applied after the Doff pin has been driven High in order to ensure that the DLL locks properly (and the DLL must lock
properly before issuing read and write commands). However, tKInit is greater than tKLock, even at the slowest permitted cycle time
of 8.4 ns (2048*8.4 ns = 17.2
s). Consequently, the 20 s associated with tKInit is sufficient to cover the tKLock requirement at
power-up if the Doff pin is driven High prior to the start of the 20
s period.
Also, tKInit only needs to be met once, immediately after power-up, whereas tKLock must be met any time the DLL is disabled/reset
(whether by toggling Doff Low or by stopping K clocks for > 30 ns).
SigmaQuad-II B2 Coherency and Pass Through Functions
Because the SigmaQuad-II B2 read and write commands are loaded at the same time, there may be some confusion over what
constitutes “coherent” operation. Normally, one would expect a RAM to produce the just-written data when it is read immediately
after a write. This is true of the SigmaQuad-II B2 except in one case, as is illustrated in the following diagram. If the user holds the
same address value in a given K clock cycle, loading the same address as a read address and then as a matching write address, the
SigmaQuad-II B2 will read or “Pass-thru” the latest data input, rather than the data from the previously completed write operation.


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