CS4970x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

DS752F1

6

• OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external memory,

processing host messages, calling audio-processing subroutines, auto-detection, error concealment, etc.

the decoding/processing algorithms listed require delivery of PCM or IEC61937-packed, compressed data

• Matrix-processors - Any module that processes audio I/O buffer PCM data in-place before the Post-

processors. Generally speaking, these modules alter the number of valid channels in the audio I/O buffer

through processes like Virtualization (n

2 channels) or Matrix Decoding (2n channels). Examples are

Dolby ProLogic IIx and DTS Neo:6.

• Virtualizer-processor - Any module that encodes PCM data into fewer output channels than input

channels (n

2 channels) with the effect of providing “phantom” speakers to represent the physical audio

channels that were eliminated. Examples are Dolby Headphone 2 and Dolby Virtual Speaker 2. Generally

speaking, these modules reduce the number of valid channels in the audio I/O buffer.

• Post-processors - Any module that processes audio I/O buffer PCM data in-place after the matrix

processors. Examples are bass management, audio manager, tone control, EQ, delay, customer-specific

effects, Dolby Headphone/Virtual Speaker, etc.

The overlay structure reduces the time required to reconfigure the DSP when a processing change is

requested. Each overlay can be reloaded independently without disturbing the other overlays. For example,

when a new decoder is selected, the OS, matrix-, and post-processors do not need to be reloaded — only the

new decoder (the same is true for the other overlays).

4 Hardware Functional Description

4.1 Coyote DSP Core

The CS4970x4 is a dual-core Coyote DSP with separate X and Y data and P code memory spaces. Each core

is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two multiply

accumulate (MAC) operations per clock cycle. Each core has eight 72-bit accumulators, four X- and four Y-data

registers, and 12 index registers.

Both DSP cores are coupled to a flexible DMA engine. The DMA engine can move data between peripherals

such as the digital audio input (DAI) and digital audio output (DAO), external memory, or any DSP core

memory, all without the intervention of the DSP. The DMA engine offloads data move instructions from the DSP

core, leaving more MIPS available for signal processing instructions.

CS4970x4 functionality is controlled by application codes that are stored in on-board ROM or downloaded to

the CS4970x4 from a host MCU or external FLASH/EEPROM. Users can choose to use standard audio

decoder and post-processor modules which are available from Cirrus Logic.

The CS4970x4 is suitable for audio decoder, audio post-processor, audio encoder, DVD audio/video player,

and digital broadcast decoder applications.

4.1.1 DSP Memory

Each DSP core has its own on-chip data and program RAM and ROM and does not require external memory

for any of today’s popular audio algorithms including Dolby Digital Surround EX, AAC Multichannel, DTS-ES

96/24, and THX Ultra2. However, if the end-system design requires support of the new high-definition audio

formats, external SDRAM will be needed to support Dolby TrueHD and DTS-HD master audio.

The memory maps for the DSPs are as follows. All memory sizes are composed of 32-bit words.