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CS4399 Fiches technique(PDF) 8 Page - Cirrus Logic

No de pièce CS4399
Description  130-dB, 32-Bit High-Performance DAC
Download  111 Pages
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Fabricant  CIRRUS [Cirrus Logic]
Site Internet  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS4399 Fiches technique(HTML) 8 Page - Cirrus Logic

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DS1113F1
CS4399
1.4 Electrostatic Discharge (ESD) Protection Circuitry
1.4 Electrostatic Discharge (ESD) Protection Circuitry
Fig. 1-3 provides a composite view of the ESD domains showing the ESD protection paths between each pad and the
substrate (GND), as well as the interrelations between some domains. Note that this figure represents the structure for the
internal protection devices and that additional protections can be implemented as part of the integration into the board.
Figure 1-3. Composite ESD Topology
Table 1-2 shows the individual ESD domains and lists the pins associated with each domain.
ESD-sensitive device. The CS4399 is manufactured on a CMOS process. Therefore, it is generically
susceptible to damage from excessive static voltages. Proper ESD precautions must be taken while
handling and storing this device. This device is qualified to current JEDEC ESD standards.
Table 1-2. ESD Domains
ESD Domain
Signal Name
(See * in Topology Figures for Pad)
Topology
VL/GNDD
ADR
DSDCLK/SCLK2
SCL
SDA
DSDB/LRCK2
DSDA/SDIN2
SDIN1
LRCK1
SCLK1
CLKOUT
XTI/MCLK
XTO
VL
GNDD
Substrate
VD
VA
–VA
VP
*
*
VCP_FILT+
GNDCP
VCP_FILT–
*
*
VCP
GNDA
VP/GNDCP Domain
VP/VCP_FILT– Domain
VCP_FILT+/VCP_FILT– Domain
*
VL
GNDD
Substrate
*


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