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HT48R002 Fiches technique(PDF) 26 Page - Holtek Semiconductor Inc |
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HT48R002 Fiches technique(HTML) 26 Page - Holtek Semiconductor Inc |
26 / 71 page Rev. 1.11 26 April 11, 2017 Rev. 1.11 27 April 11, 2017 HT48R002/HT48R003 Cost-Effective I/O 8-Bit OTP MCU HT48R002/HT48R003 Cost-Effective I/O 8-Bit OTP MCU Watchdog Timer Operation TheWatchdogTimeroperatesbyprovidingadeviceresetwhenitstimeroverflows.Thismeans thatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallyclearthe WatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisis doneusingtheclearwatchdoginstruction.NotethatiftheWatchdogTimerfunctionisnotenabled, thenanyinstructionrelatedtotheWatchdogTimerwillresultinnooperation. SettingthevariousWatchdogTimeroptionsarecontrolledviatheinternalregistersWDTCand WDTS.EnablingtheWatchdogTimercanbecontrolledbytheWDTENbitsintheinternalWDTC registerintheDataMemory. TheWatchdogTimerwillbedisabledifbitsWDTEN5~WDTEN0intheWDTCregisterarewritten withthebinaryvalue101101BwhiletheWDTTimerwillbeenabledifthesebitsarewritten withthebinaryvalue000000B.Ifthesebitsarewrittenwiththeothervaluesexcept000000Band 101101B,theMCUwillbereset. TheWatchdogTimer clock can emanate from three different sources, selected by the WDTCLS1~WDTCLS0bitsintheWDTCregister.ThesesourcesarefSYS,fSYS/4orLIRC.Itis importanttonotethatwhenthesystementerstheSleepModetheinstructionclockisstopped, thereforeifithasselectedfSYSorfSYS/4astheWatchdogTimerclocksource,theWatchdogTimer willstop.Forsystemsthatoperateinnoisyenvironments,it’srecommendedtousetheLIRCas theclocksource.Thedivisionratiooftheprescalerisdeterminedbybits0,1and2oftheWDTS register,knownasWS0,WS1andWS2.IftheWatchdogTimerinternalclocksourceisselectedand withtheWS0,WS1andWS2bitsoftheWDTSregisterallsethigh,theprescalerdivisionratiowill be1:32768,whichwillgiveamaximumtime-outperiod. Undernormalprogramoperation,aWatchdogTimertime-outwillinitializeadeviceresetandset thestatusbitTO.However,ifthesystemisintheSleepMode,whenaWatchdogTimertime-out occurs,thedevicewillbewokenup,theTObitinthestatusregisterwillbesetandonlytheProgram CounterandStackPointerwillbereset.Fourmethodscanbeadoptedtoclearthecontentsofthe WatchdogTimer.ThefirstisaWDTsoftwarereset,whichmeansacertainvalueexcept101101B and000000BwrittenintotheWDTENbitfiled,thesecondisanexternalhardwarereset,which meansalowlevelontheexternalresetpin,thethirdisusingtheClearWatchdogTimersoftware instructionsandthefourthisviaa“HALT”instruction. ThereisonlyonemethodofusingsoftwareinstructiontocleartheWatchdogTimer.Thatistouse the“CLRWDT”instructiontocleartheWDT. “ CLR WDT”Instruction WDT Divider WDTEN bits Reset MCU fS 8-to-1 MUX CLR WS2~WS0 WDT Time-out (28/fS ~ 215/fS) LIRC M U X WDTCLS1, WDTCLS0 “ HALT”Instruction RES pin reset fSYS fSYS/4 8-stage Prescaler fS/8 Watchdog Timer |
Numéro de pièce similaire - HT48R002 |
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Description similaire - HT48R002 |
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