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S124 Fiches technique(PDF) 43 Page - Renesas Technology Corp |
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S124 Fiches technique(HTML) 43 Page - Renesas Technology Corp |
43 / 98 page R01DS0264EU0100 Rev.1.00 Page 43 of 95 Feb 23, 2016 S124 2. Electrical Characteristics 2.3.3 Reset Timing Note 1. When OFS1.LVDAS = 0. Note 2. When OFS1.LVDAS = 1. Note 3. When IWDTCR.CKS[3:0] = 0000b. Figure 2.22 Reset input timing at power-on Figure 2.23 Reset input timing (1) Table 2.22 Reset timing Item Symbol Min Typ Max Unit Test conditions RES pulse width At power-on tRESWP 3- - ms Figure 2.22 Not at power-on tRESW 30 - - μs Figure 2.23 Wait time after RES cancellation (at power-on) LVD0 enabled*1 tRESWT -0.7 - ms Figure 2.22 LVD0 disabled*2 -0.3 - Wait time after RES cancellation (during powered-on state) LVD0 enabled*1 tRESWT2 -0.5 - μs Figure 2.23 LVD0 disabled*2 -0.05 - Reset period IWDT*3 tRESWIW -1 - IWDT clock cycle Figure 2.24 Internal reset (except IWDT) tRESWIR -1 - ICLK cycle Wait time after internal reset cancellation LVD0 enabled*1 tRESWT3 -0.5 - μs LVD0 disabled*2 -0.05 - VCC RES tRESWP Internal reset tRESWT RES Internal reset tRESWT2 tRESW |
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Description similaire - S124 |
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