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TP3070J Fiches technique(PDF) 8 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No de pièce TP3070J
Description  COMBO II Programmable PCM CODEC/Filter
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Fabricant  NSC [National Semiconductor (TI)]
Site Internet  http://www.national.com
Logo NSC - National Semiconductor (TI)

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Programmable Functions (Continued)
and convert to the binary equivalent. Some examples are
given in
Table 7 and a complete tabulation is given in Appen-
dix I of AN-614.
It should be noted that the Transmit (idle channel) Noise and
Transmit Signal to Total Distortion are both specified with
transmit gain set to 0 dB (Gain Register set to all ones). At
high transmit gains there will be some degradation in noise
performance for these parameters. See Application Note
AN-614 for more information on this subject.
TABLE 7. Byte 2 of Transmit Gain Instruction
Bit Number
0 dBm0 Test Level (Vrms)
76543210
at VF
XI
00000000
No Output (Note 8)
00000001
0.087
00000010
0.088
——
11111110
1.600
11111111
1.619
Note 8: Analog signal path is cut off, but DX remains active and will output
codes representing idle noise.
8.0 RECEIVE GAIN INSTRUCTION BYTE 2
The receive gain can be programmed in 0.1 dB steps by writ-
ing to the Receive Gain Register as defined in
Table 1 and
Table 8. Note the following restrictions on output drive capa-
bility:
a) 0 dBm0 levels
≤ 1.96 Vrms at VF
RO may be driven into
a load of
≥ 15 kΩ to GND; receive gain set to 0 dB (Gain
Register set to all ones)
b) 0 dBm0 levels
≤ 1.85 Vrms at VF
RO may be driven into
a load of
≥ 600Ω to GND; receive gain set to −0.5 dB
c) 0 dBm0 levels
≤ 1.71 Vrms at VF
RO may be driven into
a load of
≥ 300Ω to GND; receive gain set to −1.2 dB
To calculate the binary code for byte 2 of this instruction for
any desired output 0 dBm0 level in Vrms, take the nearest in-
teger to the decimal number given by:
200 x log
10 (V/0.1043)
and convert to the binary equivalent. Some examples are
given in
Table 8 and a complete tabulation is given in Appen-
dix I of AN-614.
TABLE 8. Byte 2 of Receive Gain Instruction
Bit Number
0 dBm0 Test Level (Vrms)
76543210
at VF
RO
00000000
No Output (Low Z to GND)
00000001
0.105
00000010
0.107
——
11111110
1.941
11111111
1.964
9.0 HYBRID BALANCE FILTER
The Hybrid Balance Filter on COMBO II is a programmable
filter consisting of a second-order section, Hybal1, followed
by a first-order section, Hybal2, and a programmable attenu-
ator. Either of the filter sections can be bypassed if only one
is required to achieve good cancellation. A selectable 180
degree inverting stage is included to compensate for inter-
face circuits which also invert the transmit input relative to
the receive output signal. The 2nd order section is intended
mainly to balance low frequency signals across a trans-
former SLIC, and the first order section to balance midrange
to higher audio frequency signals.
As a 2nd order section, Hybal1 has a pair of low frequency
zeroes and a pair of complex conjugate poles. When config-
uring Hybal1, matching the phase of the hybrid at low to
mid-band frequencies is most critical. Once the echo path is
correctly balanced in phase, the magnitude of the cancella-
tion signal can be corrected by the programmable attenua-
tor.
The 2nd order mode of Hybal1 is most suitable for balancing
interfaces with transformers having high inductance of 1.5
Henries or more. An alternative configuration for smaller
transformers is available by converting Hybal1 to a simple
first-order section with a single real low-frequency pole and
zero. In this mode, the pole/zero frequency may be pro-
grammed.
Many line interfaces can be adequately balanced by use of
the Hybal1 section only, in which case the Hybal2 filter
should be de-selected to bypass it.
Hybal2, the higher frequency first-order section, is provided
for balancing an electronic SLIC, and is also helpful with a
transformer SLIC in providing additional phase correction for
mid and high-band frequencies, typically 1 kHz to 3.4 kHz.
Such a correction is particularly useful if the test balance im-
pedance includes a capacitor of 100 nF or less, such as the
loaded and non-loaded loop test networks in the United
States. Independent placement of the pole and zero location
is provided.
Figure 2 shows a simplified diagram of the local echo path
for a typical application with a transformer interface. The
magnitude and phase of the local echo signal, measured at
VF
XI, are a function of the termination impedance ZT, the line
transformer and the impedance of the 2W loop, Z
L. If the im-
pedance reflected back into the transformer primary is ex-
pressed as Z
L' then the echo path transfer function from
VF
ROtoVFXI is:
H(w) = Z
L'/(ZT +ZL')
(1)
9.1 PROGRAMMING THE FILTER
On initial power-up, the Hybrid Balance filter is disabled. Be-
fore the hybrid balance filter can be programmed it is neces-
sary to design the transformer and termination impedance in
order to meet system 2W input return loss specifications,
which are normally measured against a fixed test impedance
(600 or 900
Ω in most countries). Only then can the echo
path be modeled and the hybrid balance filter programmed.
Hybrid balancing is also measured against a fixed test im-
pedance, specified by each national Telecom administration
to provide adequate control of talker and listener echo over
the majority of their network connections. This test imped-
ance is Z
L in Figure 2. The echo signal and the degree of
transhybrid loss obtained by the programmable filter must be
measured from the PCM digital input, D
R0, to the PCM digi-
tal output, D
X0, either by digital test signal analysis or by
conversion back to analog by a PCM CODEC/Filter.
www.national.com
8


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