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TP3076J Fiches technique(PDF) 10 Page - National Semiconductor (TI) |
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TP3076J Fiches technique(HTML) 10 Page - National Semiconductor (TI) |
10 / 18 page Electrical Characteristics (Continued) Note 13: See definitions and timing conventions section. Timing Specifications Unless otherwise noted, limits printed in BOLD characters are guaranteed for V CC = +5V ±5%;VBB = −5V ±5%;TA = 0˚C to +70˚C by correlation with 100% electrical testing at T A = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at V CC = +5V, VBB = −5V, T A = 25˚C. All timing parameters are measured at V OH = 2.0V and VOL = 0.7V. See Definitions and Timing Conventions section for test methods information. Symbol Parameter Conditions Min Typ Max Units MASTER CLOCK TIMING f MCLK Frequency of MCLK Selection of Frequency is Programmable 512 kHz (See Table 5) 1536 kHz 1544 kHz 2048 kHz 4096 kHz t WMH Period of MCLK High Measured from V IH to VIH (Note 14) 80 ns t WML Period of MCLK Low Measured from V IL to VIL (Note 14) 80 ns t RM Rise Time of MCLK Measured from V IL to VIH 30 ns t FM Fall Time of MCLK Measured from V IH to VIL 30 ns t HBM HOLD Time, BCLK LOW 50 ns to MCLK HIGH t WFL Period of FS X Measured from V IL to VIL 1 MCLK or FS R Low Period PCM INTERFACE TIMING f BCLK Frequency of BCLK May Vary from 64 kHz to 4096 kHz 64 4096 kHz in 8 kHz Increments t WBH Period of BCLK High Measured from V IH to VIH 80 ns t WBL Period of BCLK Low Measured from V IL to VIL 80 ns t RB Rise Time of BCLK Measured from V IL to VIH 30 ns t FB Fall Time of BCLK Measured from V IH to VIL 30 ns t HBF Hold Time, BCLK Low 30 ns to FS X/R High or Low t SFB Setup Time, FS X/R 30 ns High to BCLK Low t DBD Delay Time, BCLK High Load = 100 pF Plus 2 LSTTL Loads 80 ns to Data Valid t DBZ Delay Time, BCLK Low to D X1DX1 disabled is measured Disabled if FS X Low, FSX Low to at V OL or VOH according D X1 disabled if 8th BCLK to Figure 5 15 80 ns Low, or BCLK High to D X1 Disabled if FS X High t DBT Delay Time, BCLK High to Load = 100 pF Plus 2 LSTTL Loads TS X Low if FSX High, or 60 ns FS X High to TSX Low if BCLK High (Nondelayed mode); BCLK High to TS X Low (delayed data mode) t ZBT TRI-STATE Time, BCLK Low to TS X High if FSX Low, FSX Low to TS X High if 8th BCLK Low, or 15 60 ns BCLK High to TS X High if FSX High t DFD Delay Time, FS X/R Load = 100 pF Plus 2 LSTTL Loads, www.national.com 10 |
Numéro de pièce similaire - TP3076J |
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Description similaire - TP3076J |
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