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Si1002-E-GM2 Fiches technique(PDF) 7 Page - Silicon Laboratories |
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Si1002-E-GM2 Fiches technique(HTML) 7 Page - Silicon Laboratories |
7 / 382 page Rev. 1.3 7 Si1000/1/2/3/4/5 List of Figures Figure 1.1. Si1000 Block Diagram ........................................................................... 18 Figure 1.2. Si1001 Block Diagram ........................................................................... 18 Figure 1.3. Si1002 Block Diagram ........................................................................... 19 Figure 1.4. Si1003 Block Diagram ........................................................................... 19 Figure 1.5. Si1004 Block Diagram ........................................................................... 20 Figure 1.6. Si1005 Block Diagram ........................................................................... 20 Figure 1.7. Si1002/3 RX/TX Direct-tie Application Example .................................... 21 Figure 1.8. Si1000/1 Antenna Diversity Application Example ................................. 21 Figure 1.9. Port I/O Functional Block Diagram ........................................................ 23 Figure 1.10. PCA Block Diagram ............................................................................. 24 Figure 1.11. ADC0 Functional Block Diagram ......................................................... 25 Figure 1.12. ADC0 Multiplexer Block Diagram ........................................................ 26 Figure 1.13. Comparator 0 Functional Block Diagram ............................................ 27 Figure 1.14. Comparator 1 Functional Block Diagram ............................................ 27 Figure 3.1. Si100/1/2/3-E-GM2 Pinout Diagram (Top View) ................................... 33 Figure 3.2. Si1004/5-E-GM2 Pinout Diagram (Top View) ....................................... 34 Figure 3.3. LGA-42 Package Drawing (Si1000/1/2/3/4/5-E-GM2) ........................... 35 Figure 3.4. LGA-42 PCB Land Pattern Dimensions (Si1000/1/2/3/4/5-E-GM2) ...... 37 Figure 3.5. LGA-42 PCB Stencil and Via Placement ............................................... 39 Figure 4.1. Active Mode Current (External CMOS Clock) ....................................... 44 Figure 4.2. Idle Mode Current (External CMOS Clock) ........................................... 45 Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 2 V ............................................................. 46 Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 3 V) ............................................................ 47 Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC+ = 2 V) ............................................................. 48 Figure 4.6. Typical One-Cell Suspend Mode Current .............................................. 49 Figure 4.7. Typical VOH Curves, 1.8–3.6 V ............................................................ 51 Figure 4.8. Typical VOH Curves, 0.9–1.8 V ............................................................ 52 Figure 4.9. Typical VOL Curves, 1.8–3.6 V ............................................................. 53 Figure 4.10. Typical VOL Curves, 1.8–3.6 V ........................................................... 54 Figure 4.11. Typical VOL Curves, 0.9–1.8 V ........................................................... 55 Figure 5.1. ADC0 Functional Block Diagram ........................................................... 74 Figure 5.2. 10-Bit ADC Track and Conversion Example Timing (BURSTEN = 0) ..................................................................................... 77 Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4 .................. 79 Figure 5.4. ADC0 Equivalent Input Circuits ............................................................. 80 Figure 5.5. ADC Window Compare Example: Right-Justified Single-Ended Data ................................................................................ 90 Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data ................................................................................ 90 Figure 5.7. ADC0 Multiplexer Block Diagram .......................................................... 91 |
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