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CDCVF857RHATG4 Fiches technique(PDF) 7 Page - Texas Instruments

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No de pièce CDCVF857RHATG4
Description  2.5-V PHASE-LOCKED-LOOP CLOCK DRIVER
Download  23 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

CDCVF857RHATG4 Fiches technique(HTML) 7 Page - Texas Instruments

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TIMING REQUIREMENTS
SWITCHING CHARACTERISTICS
CDCVF857
SCAS047F – MARCH 2003 – REVISED MAY 2007
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
Part-to-part input
∆C
VDDQ = 2.5 V, VI = VDDQ or GND
1
pF
capacitance variation
Input capacitance difference
CI(∆)
between CLK and CLK,
VDDQ = 2.5 V, VI = VDDQ or GND
0.25
pF
FBIN, and FBIN
over recommended ranges of supply voltage and operating free-air temperature
PARAMETER
MIN
MAX
UNIT
Operating clock frequency
60
220
fCLK
MHz
Application clock frequency
90
220
Input clock duty cycle
40%
60%
Stabilization time (PLL mode) (1)
10
µs
Stabilization time (bypass mode) (2)
30
ns
(1)
The time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be
obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK and VDD must be applied. Until phase lock is obtained,
the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This
parameter does not apply for input modulation under SSC application.
(2)
A recovery time is required when the device goes from power-down mode into bypass mode (AVDD at GND).
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH(1)
Low-to-high level propagation delay time
Test mode/CLK to any output
3.5
ns
tPHL(1)
High-to-low level propagation delay time
Test mode/CLK to any output
3.5
ns
100 MHz (PC1600)
–65
65
tjit(per)(2)
Jitter (period), see Figure 7
ps
133/167/200 MHz (PC2100/2700/3200)
–30
30
100 MHz (PC1600)
–50
50
tjit(cc)(2)
Jitter (cycle-to-cycle), see Figure 4
ps
133/167/200 MHz (PC2100/2700/3200)
–35
35
100 MHz (PC1600)
–100
100
tjit(hper)(2)
Half-period jitter, see Figure 8
ps
133/167/200 MHz (PC2100/2700/3200)
–75
75
tslr(o)
Output clock slew rate, see Figure 9
Load: 120
Ω, 14 pF
1
2
V/ns
t(φ)
Static phase offset, see Figure 5
100/133/167/200 MHz
–50
50
ps
tsk(o)
Output skew, see Figure 6
Load: 120
Ω, 14 pF; 100/133/167/200 MHz
40
ps
(1)
Refers to the transition of the noninverting output.
(2)
This parameter is assured by design but cannot be 100% production tested.
7
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