CDCM61004

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SCAS871H – FEBRUARY 2009 – REVISED JANUARY 2016

7.7 Typical Output Jitter Characteristics

(1)

OUTPUT

LVCMOS OUTPUT

LVPECL OUTPUT

LVDS OUTPUT

FREQUENCY

INPUT (MHz)

(MHz)

62.5

25

592

32.9

611

20.7

667

28.4

75

25

518

27.5

533

19.4

572

25.7

77.76

24.8832

506

29.2

526

20.9

567

26.9

100

25

507

24.5

510

20.7

533

26.5

106.25

26.5625

535

23.5

524

20.2

553

26.5

125

25

557

39.6

556

21.4

570

27.1

150

25

518

38.4

493

18.9

515

26.2

155.52

24.8832

498

36.9

486

19.8

502

26.7

156.25

25

510

37.7

503

20.7

518

26.5

159.375

26.5625

535

37.4

510

19.9

534

26.3

187.5

25

506

32.8

506

20.3

509

25.5

200

25

491

23.3

492

30

499

34.9

212.5

26.5625

520

47.8

509

30.8

530

37.3

250

25

544

27.4

541

21.4

550

27.5

311.04

24.8832

481

20.5

496

24.7

312.5

25

501

20.8

508

25.8

622.08

24.8832

492

27.2

500

27.2

625

25

515

26.9

509

27

(1)

Figure 8, Figure 10, and Figure 12 show LVCMOS, LVPECL, and LVDS test setups (respectively) using appropriate quartz crystal in,

7.8 Crystal Characteristics

PARAMETER

MIN

TYP

MAX

UNIT

Mode of oscillation

Fundamental

MHz

Frequency

21.875

28.47

MHz

Equivalent series resistance (ESR)

50

Ω

On-chip load capacitance

8

10

pF

Drive level

0.1

1

mW

Maximum shunt capacitance

7

pF

7.9 Dissipation Ratings

(1) (2)

VALUE

TEST

PARAMETER

UNIT

4 × 4 VIAS

CONDITIONS

ON PAD

Thermal resistance, junction-to-ambient

0 LFM

35

°C/W

(3)

Thermal resistance, junction-to-pad

4

°C/W

(1)

The package thermal resistance is calculated in accordance with JESD 51 and JEDEC 2S2P (high-K board).

(2)

Connected to GND with nine thermal vias (0.3-mm diameter).

(3)

package.

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