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MC100EP451FAR2 Fiches technique(PDF) 1 Page - ON Semiconductor |
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MC100EP451FAR2 Fiches technique(HTML) 1 Page - ON Semiconductor |
1 / 10 page © Semiconductor Components Industries, LLC, 2004 June, 2004 − Rev. 6 1 Publication Order Number: MC10EP451/D MC10EP451, MC100EP451 3.3V / 5VECL 6−Bit Differential Register with Master Reset The MC10/100EP451 is a 6−bit fully differential register with common clock and single−ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All inputs have a 75 k W pulldown resistor internally. Differential inputs have an override clamp. Unused differential register inputs can be left open and will default LOW. When the differential inputs are forced to < VEE + 1.2 V, the clamp will override and force the output to a default state. When in the default state, and since the flip−flop is edge triggered, the output reaches a determined, but not predicted, valid state. The positive transition of CLK (pin 4) will latch the registers. Master Reset (MR) HIGH will asynchronously reset all registers forcing Q outputs to go LOW. The 100 Series contains temperature compensation. • 450 ps Typical Propagation Delay • Maximum Frequency > 3.0 GHz Typical • Asynchronous Master Reset • 20 ps Skew Within Device, 35 ps Skew Device−To−Device • PECL Mode Operating Range: V CC = 3.0 V to 5.5 V With VEE = 0 V • NECL Mode Operating Range: V CC = 0 V With VEE = −3.0 V to −5.5 V • Open Input Default State • Safety Clamp on Inputs • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. LQFP−32 FA SUFFIX CASE 873A MARKING DIAGRAM* MCxxx AWLYYWW xxx = 10 or 100 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week EP451 1 32 http://onsemi.com See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. ORDERING INFORMATION *For additional marking information, refer to Application Note AND8002/D. |
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