Moteur de recherche de fiches techniques de composants électroniques |
|
AK4376AECB Fiches technique(PDF) 34 Page - Asahi Kasei Microsystems |
|
AK4376AECB Fiches technique(HTML) 34 Page - Asahi Kasei Microsystems |
34 / 68 page [AK4376A] 016014206-E-00 2016/11 - 34 - 2. PLL Feedback Clock Divider The dividing number of feedback clock can be set freely in 16-bit. PLLCLK is divided by (PLM +1) and used as PLL feedback clock. The feedback clock is fixed to “L” without dividing when PLM[15:0] bits = 0000H. Table 9. PLL Feedback Clock Divider PLM[15:0] bits Dividing Number 0000H Clock Stop (default) 0001H to FFFFH 1 / (PLM + 1) 3. Power Management (PMPLL) PLL can be powered down by a control register setting. Table 10. PLL Power Control PMPLL bit PLL Status 0 Power-Down (default) 1 Power-Up |
Numéro de pièce similaire - AK4376AECB |
|
Description similaire - AK4376AECB |
|
|
Lien URL |
Politique de confidentialité |
ALLDATASHEET.FR |
ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |