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AK4376AECB Fiches technique(PDF) 34 Page - Asahi Kasei Microsystems

No de pièce AK4376AECB
Description  Low-Power Advanced 32-bit DAC with HP
Download  68 Pages
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Fabricant  AKM [Asahi Kasei Microsystems]
Site Internet  http://www.akm.com
Logo AKM - Asahi Kasei Microsystems

AK4376AECB Fiches technique(HTML) 34 Page - Asahi Kasei Microsystems

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[AK4376A]
016014206-E-00
2016/11
- 34 -
2. PLL Feedback Clock Divider
The dividing number of feedback clock can be set freely in 16-bit. PLLCLK is divided by (PLM +1) and used
as PLL feedback clock.
The feedback clock is fixed to “L” without dividing when PLM[15:0] bits = 0000H.
Table 9. PLL Feedback Clock Divider
PLM[15:0] bits
Dividing Number
0000H
Clock Stop
(default)
0001H to FFFFH
1 / (PLM + 1)
3. Power Management (PMPLL)
PLL can be powered down by a control register setting.
Table 10. PLL Power Control
PMPLL bit
PLL Status
0
Power-Down
(default)
1
Power-Up


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