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ADE7754AR Fiches technique(PDF) 3 Page - Analog Devices |
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ADE7754AR Fiches technique(HTML) 3 Page - Analog Devices |
3 / 44 page REV. PrG 01/03 PRELIMINARY TECHNICAL DATA –3– ADE7754 ADE7754TIMINGCHARACTERISTICS1,2 Parameter Units Test Conditions/Comments Write timing t1 50 ns (min) CS falling edge to first SCLK falling edge t2 50 ns (min) SCLK logic high pulse width t3 50 ns (min) SCLK logic low pulse width t4 10 ns (min) Valid Data Set up time before falling edge of SCLK t5 5 ns (min) Data Hold time after SCLK falling edge t6 400 ns (min) Minimum time between the end of data byte transfers. t7 50 ns (min) Minimum time between byte transfers during a serial write. t8 100 ns (min) CS Hold time after SCLK falling edge. Read timing t9 5 4 µs (min) Minimum time between read command (i.e. a write to Communication Register) and data read. t10 50 ns (min) Minimum time between data byte transfers during a multibyte read. t11 3 30 ns (min) Data access time after SCLK rising edge following a write to the Communications Register t12 4 100 ns (max) Bus relinquish time after falling edge of SCLK. 10 ns (min) t13 4 100 ns (max) Bus relinquish time after rising edge of CS. 10 ns (min) SerialReadTiming Serial Write Timing CS SCLK DIN A4 A3 A2 A1 A0 DB7 Most Significant Byte t1 t2 t3 t4 t5 t8 1 DB0 DB7 DB0 t6 Least Significant Byte t7 t7 0 Command Byte A5 CS SCLK DIN A4 A3 A2 A1 A0 t1 t11 t12 t9 DB7 DOUT t13 DB0 DB0 DB7 t10 t14 Most Significant Byte Least Significant Byte 00 Command Byte A5 (AVDD = DVDD = 5V ± 5%, AGND = DGND = 0V, On-Chip Reference, CLKIN = 10MHz XTAL, TMIN to TMAX = -40°C to +85°C) Figure 1 - Load Circuit for Timing Specifications 200 µA 1.6 mA IOH IOL CL 50pF TO OUTPUT PIN +2.1V NOTES 1 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5ns (10% to 90%) and timed from a voltage level of 1.6V. 2 See timing diagram below and Serial Interface section of this data sheet. 3 Measured with the load circuit in Figure 1 and defined as the time required for the output to cross 0.8V or 2.4V. 4 Derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit in Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 5Minimum time between read command and data read for all registers except WAVFORM register. For WAVFORM register t9=500ns min |
Numéro de pièce similaire - ADE7754AR |
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Description similaire - ADE7754AR |
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