MB85RC04VPNF-G datasheet(4/29 Pages) FUJITSU

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MB85RC04VPNF-G Fiches technique(PDF) 4 Page - Fujitsu Component Limited.

No de pièce	MB85RC04VPNF-G

Description	4 K (512 횞 8) Bit I2C

Download	29 Pages

Scroll/Zoom	100%

Fabricant	FUJITSU [Fujitsu Component Limited.]

Site Internet	http://edevice.fujitsu.com/fmd/en/index.html

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4 / 29 page

MB85RC04V

DS501-00016-2v0-E

■ I2C COMMUNICATION PROTOCOL

The I2C bus is a two wire serial interface that uses a bidirectional data bus (SDA) and serial clock (SCL). A

data transfer can only be initiated by the master, which will also provide the serial clock for synchronization.

The SDA signal should change while SCL is the “L” level. However, as an exception, when starting and

stopping communication sequence, SDA is allowed to change while SCL is the “H” level.

• Start Condition

To start read or write operations by the I2C bus, change the SDA input from the “H” level to the “L” level while

the SCL input is in the “H” level.

• Stop Condition

To stop the I2C bus communication, change the SDA input from the “L” level to the “H” level while the SCL

input is in the “H” level. In the reading operation, inputting the stop condition finishes reading and enters the

standby state. In the writing operation, inputting the stop condition finishes inputting the rewrite data and

enters the standby state.

• Start Condition, Stop Condition

Note : At the write operation, the FRAM device does not need the programming wait time (tWC) after issuing the

Stop Condition.

SCL

SDA

Start

Stop

H or L

Fabricant	No de pièce	Fiches technique	Description
Fujitsu Component Limit...	MB85RC04V	307Kb / 29P	4 K (512 횞 8) I2C

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