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FAN4810MX Fiches technique(PDF) 2 Page - Fairchild Semiconductor |
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FAN4810MX Fiches technique(HTML) 2 Page - Fairchild Semiconductor |
2 / 14 page FAN4810 PRODUCT SPECIFICATION 2 REV. 1.0.12 9/24/03 Pin Configuration Pin Description Pin Name Function 1 IEAO Slew rate enhanced PFC transconductance error amplifier output 2IAC PFC AC line reference input to Gain Modulator 3ISENSE Current sense input to the PFC Gain Modulator 4VRMS PFC Gain Modulator RMS line voltage compensation input 5 CLKSD Turn on/off PWM clock without disturbing PFC out 6NC 7 RAMP 1 Oscillator timing node; timing set by RTCT 8NC 9 GND Ground 10 GND Ground 11 CLK OUT Clock signal synchronized to PFC frequency 12 PFC OUT PFC driver output 13 VCC Positive supply 14 VREF Buffered output for the internal 7.5V reference 15 VFB PFC transconductance voltage error amplifier input 16 VEAO PFC transconductance voltage error amplifier output 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 IEAO IAC ISENSE VRMS CLKSD NC RAMP 1 NC VEAO VFB VREF VCC PFC OUT CLK OUT GND GND TOP VIEW FAN4810 (Pin Out) |
Numéro de pièce similaire - FAN4810MX |
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Description similaire - FAN4810MX |
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