Moteur de recherche de fiches techniques de composants électroniques
  French  ▼
ALLDATASHEET.FR

X  

STK15C68-W35 Fiches technique(PDF) 7 Page - List of Unclassifed Manufacturers

No de pièce STK15C68-W35
Description  8K x 8 AutoStore nvSRAM
Download  9 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricant  ETC [List of Unclassifed Manufacturers]
Site Internet  
Logo ETC - List of Unclassifed Manufacturers

STK15C68-W35 Fiches technique(HTML) 7 Page - List of Unclassifed Manufacturers

  STK15C68-W35 Datasheet HTML 1Page - List of Unclassifed Manufacturers STK15C68-W35 Datasheet HTML 2Page - List of Unclassifed Manufacturers STK15C68-W35 Datasheet HTML 3Page - List of Unclassifed Manufacturers STK15C68-W35 Datasheet HTML 4Page - List of Unclassifed Manufacturers STK15C68-W35 Datasheet HTML 5Page - List of Unclassifed Manufacturers STK15C68-W35 Datasheet HTML 6Page - List of Unclassifed Manufacturers STK15C68-W35 Datasheet HTML 7Page - List of Unclassifed Manufacturers STK15C68-W35 Datasheet HTML 8Page - List of Unclassifed Manufacturers STK15C68-W35 Datasheet HTML 9Page - List of Unclassifed Manufacturers  
Zoom Inzoom in Zoom Outzoom out
 7 / 9 page
background image
STK15C68
4-67
The STK15C68 is a versatile memory chip that pro-
vides several modes of operation. The STK15C68
can operate as a standard 8K x 8 SRAM. It has a 8K
x 8 EEPROM shadow to which the SRAM information
can be copied, or from which the SRAM can be
updated in nonvolatile mode.
NOISE CONSIDERATIONS
Note that the STK15C68 is a high speed memory
and so must have a high frequency bypass capaci-
tor of approximately 0.1
µF connected between DUT
V
CC and VSS, using leads and traces that are as short
as possible. As with all high speed CMOS ICs, nor-
mal careful routing of power, ground and signals will
help prevent noise problems.
SRAM READ
The STK15C68 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A
0-12 determines
which of the 8,192 data
bytes will be accessed. When the READ is initiated
by an address transition, the outputs will be valid
after a delay of t
AVQV (READ CYCLE #1). If the READ is
initiated by E or G, the outputs will be valid at t
ELQV or
at t
GLQV, whichever is later (READ CYCLE #2).
The
data outputs will repeatedly respond to address
changes within the tAVQV access time without the
need for transitions on any control input pins, and will
remain valid until another address change or until E
or G is brought high or W is brought low.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ
0-7 will be writ-
ten into the memory if it is valid t
DVWH before the end
of a W controlled WRITE or t
DVEH before the end of an
E controlled WRITE.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
WLQZ after W goes low.
SOFTWARE NONVOLATILE STORE
The STK15C68 software STORE cycle is initiated by
executing sequential READ cycles from six specific
address locations. During the STORE cycle an erase
of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements.
The program operation copies the SRAM data into
nonvolatile memory. Once a STORE cycle is initi-
ated, further input and output are disabled until the
cycle is completed.
Because
a
sequence
of
reads
from
specific
addresses is used for STORE initiation, it is impor-
tant that no other READ or WRITE accesses inter-
vene in the sequence or the sequence will be
aborted and no STORE or RECALL will take place.
To initiate the software STORE cycle, the following
READ
sequence must be performed:
1.
Read address
0000 (hex)
Valid READ
2.
Read address
1555 (hex)
Valid READ
3.
Read address
0AAA (hex)
Valid READ
4.
Read address
1FFF (hex)
Valid READ
5.
Read address
10F0 (hex)
Valid READ
6.
Read address
0F0F (hex)
Initiate STORE cycle
The software sequence is clocked with E controlled
reads.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the t
STORE cycle time has
been fulfilled, the SRAM will again be activated for
READ
and WRITE operation.
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the soft-
ware STORE initiation. To initiate the RECALL cycle,
the following sequence of READ operations must be
performed:
1.
Read address
0000 (hex)
Valid READ
2.
Read address
1555 (hex)
Valid READ
3.
Read address
0AAA (hex)
Valid READ
4.
Read address
1FFF (hex)
Valid READ
5.
Read address
10F0 (hex)
Valid READ
6.
Read address
0F0E (hex)
Initiate RECALL cycle
DEVICE OPERATION


Numéro de pièce similaire - STK15C68-W35

FabricantNo de pièceFiches techniqueDescription
logo
Simtek Corporation
STK15C68-WF25 SIMTEK-STK15C68-WF25 Datasheet
382Kb / 10P
   8K x 8 AutoStore??nvSRAM QuantumTrap??CMOS Nonvolatile Static RAM
STK15C68-WF25I SIMTEK-STK15C68-WF25I Datasheet
382Kb / 10P
   8K x 8 AutoStore??nvSRAM QuantumTrap??CMOS Nonvolatile Static RAM
STK15C68-WF35 SIMTEK-STK15C68-WF35 Datasheet
382Kb / 10P
   8K x 8 AutoStore??nvSRAM QuantumTrap??CMOS Nonvolatile Static RAM
STK15C68-WF35I SIMTEK-STK15C68-WF35I Datasheet
382Kb / 10P
   8K x 8 AutoStore??nvSRAM QuantumTrap??CMOS Nonvolatile Static RAM
STK15C68-WF45 SIMTEK-STK15C68-WF45 Datasheet
382Kb / 10P
   8K x 8 AutoStore??nvSRAM QuantumTrap??CMOS Nonvolatile Static RAM
More results

Description similaire - STK15C68-W35

FabricantNo de pièceFiches techniqueDescription
logo
Cypress Semiconductor
STK12C68 CYPRESS-STK12C68 Datasheet
751Kb / 20P
   64 Kbit (8K x 8) AutoStore nvSRAM
STK12C68-5 CYPRESS-STK12C68-5 Datasheet
591Kb / 18P
   64 Kbit (8K x 8) AutoStore nvSRAM
logo
Simtek Corporation
STK17T88 SIMTEK-STK17T88 Datasheet
581Kb / 28P
   32K x 8 AutoStore nvSRAM
logo
List of Unclassifed Man...
STK25C48 ETC-STK25C48 Datasheet
84Kb / 8P
   2K X 8 AUTOSTORE NVSRAM
logo
Simtek Corporation
STK15C68 SIMTEK-STK15C68 Datasheet
382Kb / 10P
   8K x 8 AutoStore??nvSRAM QuantumTrap??CMOS Nonvolatile Static RAM
logo
List of Unclassifed Man...
STK12C68 ETC-STK12C68 Datasheet
388Kb / 13P
   8K x 8 AutoStore??nvSRAM QuantumTrap??CMOS Nonvolatile Static RAM
STK12C68-C20 ETC-STK12C68-C20 Datasheet
125Kb / 12P
   8k x 8 AUTOSTORE NVSRAM QUANTUM TRAP CMOS NONVOLATILE STATIC RAM
STK1743 ETC-STK1743 Datasheet
253Kb / 10P
   NV TIME 8K X 8 AUTOSTORE NVSRAM WITH REAL - TIME CLOCK
logo
Cypress Semiconductor
STK14C88-5 CYPRESS-STK14C88-5 Datasheet
535Kb / 17P
   256 Kbit (32K x 8) AutoStore nvSRAM
logo
List of Unclassifed Man...
U630H64 ETC1-U630H64 Datasheet
210Kb / 14P
   HardStore 8K x 8 nvSRAM
More results


Html Pages

1 2 3 4 5 6 7 8 9


Fiches technique Télécharger

Go To PDF Page


Lien URL




Politique de confidentialité
ALLDATASHEET.FR
ALLDATASHEET vous a-t-il été utile ?  [ DONATE ] 

À propos de Alldatasheet   |   Publicité   |   Contactez-nous   |   Politique de confidentialité   |   Echange de liens   |   Fabricants
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com