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Si53119-A03AGMR Fiches technique(PDF) 4 Page - Silicon Laboratories |
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Si53119-A03AGMR Fiches technique(HTML) 4 Page - Silicon Laboratories |
4 / 34 page Si53119-A03A 4 Rev. 1.0 1. Electrical Specifications Table 1. DC Operating Characteristics VDD_A =3.3 V±5%, VDD =3.3 V±5% Parameter Symbol Test Condition Min Max Unit 3.3 V Core Supply Voltage VDD/VDD_A 3.3 V ±5% 3.135 3.465 V 3.3 V I/O Supply Voltage1 VDD_IO 1.05 V to 3.3 V ±5% 0.9975 3.465 V 3.3 V Input High Voltage VIH VDD 2.0 VDD+0.3 V 3.3 V Input Low Voltage VIL VSS-0.3 0.8 V Input Leakage Current2 IIL 0 < VIN < VDD –5 +5 µA 3.3 V Input High Voltage3 VIH_FS VDD 0.7 VDD+0.3 V 3.3 V Input Low Voltage3 VIL_FS VSS–0.3 0.35 V 3.3 V Input Low Voltage VIL_Tri 0 0.9 V 3.3 V Input Med Voltage VIM_Tri 1.3 1.8 V 3.3 V Input High Voltage VIH_Tri 2.4 VDD V 3.3 V Output High Voltage4 VOH IOH =–1mA 2.4 — V 3.3 V Output Low Voltage4 VOL IOL =1 mA — 0.4 V Input Capacitance5 CIN 2.5 4.5 pF Output Capacitance5 COUT 2.5 4.5 pF Pin Inductance LPIN —7 nH Ambient Temperature TA No Airflow 0 70 °C Notes: 1. VDD_IO applies to the low-power NMOS push-pull HCSL compatible outputs. 2. Input Leakage Current does not include inputs with pull-up or pull-down resistors. Inputs with resistors should state current requirements. 3. Internal voltage reference is to be used to guarantee VIH_FS and VIL_FS threshold levels over full operating range. 4. Signal edge is required to be monotonic when transitioning through this region. 5. Ccomp capacitance based on pad metalization and silicon device capacitance. Not including pin capacitance. |
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