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SI53112-A03A Fiches technique(PDF) 1 Page - Silicon Laboratories |
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SI53112-A03A Fiches technique(HTML) 1 Page - Silicon Laboratories |
1 / 34 page Rev. 1.0 12/15 Copyright © 2015 by Silicon Laboratories Si53112-A03A Si53112-A03A DB1200ZL 12-O UTPUT PCIE GEN 3 BUFFER Features Applications Description The Si53112-A03A is a low-power, 12-output, differential clock buffer that meets all of the performance requirements of the Intel DB1200ZL specification. To reduce board space and bill of material cost, the device fully integrates all external resistors, supporting 85 transmission lines. The device is optimized for distributing reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and 133 MHz operation. Each differential output has a dedicated hardware output enable pin for maximum flexibility and power savings. Measuring PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at www.silabs.com/pcie-learningcenter. Twelve 0.7 V low-power, push- pull, HCSL-compatible PCIe Gen 3 outputs Individual OE HW pins for each output clock 100 MHz /133 MHz PLL operation, supports PCIe and QPI PLL bandwidth SW SMBUS programming overrides the latch value from HW pin 9 selectable SMBUS addresses SMBus address configurable to allow multiple buffers in a single control network 3.3 V supply voltage operation Integrated termination resistors supporting 85 transmission lines PLL or bypass mode Spread spectrum tolerable 1.05 to 3.3 V I/O supply voltage 50 ps output-to-output skew 50 ps cyc-cyc jitter (PLL mode) Low phase jitter (Intel QPI, PCIe Gen 1/2/3/4 common clock compliant) Gen 3 SRNS Compliant 100 ps input-to-output delay Extended Temperature: –40 to 85 °C Package: 64-pin QFN For higher output devices or variations of this device, contact Silicon Labs Server Storage Data center Enterprise Switches and Routers Patents pending Ordering Information: See page 30. |
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