Si512/513

Rev. 1.0

7

Table 4. Output Clock Jitter and Phase Noise (LVPECL)

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Period Jitter

(RMS)

JPRMS

——

1.3

ps

Period Jitter

(Pk-Pk)

JPPKPK

——

11

ps

Phase Jitter

(RMS)

φJ

1.875 MHz to 20 MHz integration

—0.31

0.5

ps

12 kHz to 20 MHz integration band-

—0.8

1.0

ps

Phase Noise,

156.25 MHz

φN

100 Hz

—

–86

—

dBc/Hz

1 kHz

—

–109

—

dBc/Hz

10 kHz

—

–116

—

dBc/Hz

100 kHz

—

–123

—

dBc/Hz

1 MHz

—

–136

—

dBc/Hz

Additive RMS

Jitter Due to

External Power

JPSR

10 kHz sinusoidal noise

—

3.0

—

ps

100 kHz sinusoidal noise

—

3.5

—

ps

500 kHz sinusoidal noise

—

3.5

—

ps

1 MHz sinusoidal noise

—

3.5

—

ps

Spurious

SPR

LVPECL output, 156.25 MHz,

offset > 10 kHz

—–75

—

dBc

Notes:

1.

Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,

212.5, 250 MHz.

2.

Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.

3.

156.25 MHz. Increase in jitter on output clock due to sinewave noise added to VDD (2.5/3.3 V = 100 mVPP).