Moteur de recherche de fiches techniques de composants électroniques |
|
WM8756 Fiches technique(PDF) 12 Page - Wolfson Microelectronics plc |
|
WM8756 Fiches technique(HTML) 12 Page - Wolfson Microelectronics plc |
12 / 39 page WM8756 Advance Information AI Rev 1.3 October 2001 12 DEVICE DESCRIPTION INTRODUCTION WM8756 is a complete 6-channel stereo audio digital-to-analogue converter, including digital interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit stereo DAC and output smoothing filters. The device is implemented as three separate stereo DACs in a single package and controlled by a single interface. Each DAC has its own data input DIN0/1/2, and LRCIN, BCKIN and SCKI are shared between them. Additionally DSD compatible bitstream operation at 64x oversampling is supported on all 6 channels. Selection of normal PCM operation or this additional DSD mode is determined by the input level on the DSDB pin (14). Control of internal functionality of the device is by either hardware control (pin programmed) or software control (3-wire serial control interface). The MODE pin selects between hardware and software control. In software control mode, a 3 wire SPI type interface is used. This interface may be asynchronous to the audio data interface. Control data will be re-synchronized to the audio processing internally. Operation using a system clock of 256fs, 384fs or 512fs is provided, selection between clock rates being automatically controlled in hardware mode, or serially controlled when in software mode. Sample rates (fs) from less than 8ks/s to 96ks/s are allowed, provided the appropriate system clock is input. Support is also provided for up to 192ks/s using a system clock of 128fs or 192fs. In normal PCM mode, the audio data interface supports right, left and I 2S (Philips left justified, one bit delayed) interface formats along with a highly flexible DSP serial port interface. When in hardware mode, the three serial interface pins become control pins to allow selection of input data format type (I 2S or right justified), input word length (16, 20, 24, or 32-bit) and de-emphasis functions. In DSD mode, a separate bitstream data input pin is required for each of the 6 channels, plus a 64fs dataclock DSDCLK64. These signals are applied via separate pins (pins 3-9) and the signals multiplexed internally into the DAC circuits, under control of the DSDB mode select pin (14). Additionally in DSD mode, a Phase Modulation scheme is supported, where the audio data is transmitted as a Manchester type, bi-phase encoded bitstream. This has the advantage of removing the significant audio spectral energy from the datastream, so minimising digital signal corruption of the analogue outputs. In order to simplify decoding of this phase modulated data, a 2x speed clock (DSDCLK128) is used to sample the incoming data. This ‘modulated’ mode is auto-detected from the presence of a clock signal on the DSDCLK128 pin. In DSD mode, clocks for the DAC can be inputs (WM8756 in SLAVE mode) or outputs (WM8756 in MASTER mode). When clocks are outputs, SCKI remains an input, the lower rate clocks being derived by dividing this master clock signal. Depending upon the setting on the DMCKSEL pin, a master clock of either 256fs or 384fs may be used as input, from which the DSD clocks will be derived appropriately. AUDIO DATA SAMPLING RATES In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system’s Master Clock. The external master system clock can be applied directly through the SCKI input pin with no software configuration necessary. Note that on the WM8756, SCKI is used to derive clocks for the DAC path. The DAC path consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the DAC. The system clock for WM8756 supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The system clock is used to operate the digital filters and the noise shaping circuits. The WM8756 has a system clock detection circuit that automatically determines the relationship between the system clock frequency and the sampling rate (to within +/- 32 system clocks). If greater than 32 clocks error, the interface switches to 768fs and holds the output at the level of the last sample. The system clock should be synchronised with LRCIN, although the WM8756 is tolerant of phase differences or jitter on this clock. Table 11 shows the typical system clock frequency inputs for the WM8756. |
Numéro de pièce similaire - WM8756 |
|
Description similaire - WM8756 |
|
|
Lien URL |
Politique de confidentialité |
ALLDATASHEET.FR |
ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |