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M74VHC1GT00DTT1G Fiches technique(PDF) 1 Page - ON Semiconductor |
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M74VHC1GT00DTT1G Fiches technique(HTML) 1 Page - ON Semiconductor |
1 / 6 page © Semiconductor Components Industries, LLC, 2014 June, 2014 − Rev. 13 1 Publication Order Number: MC74VHC1GT00/D MC74VHC1GT00 Single 2-Input NAND Gate/ CMOS Logic Level Shifter LSTTL−Compatible Inputs The MC74VHC1GT00 is a single gate 2−input NAND fabricated with silicon gate CMOS technology. The internal circuit is composed of multiple stages, including a buffer output which provides high noise immunity and stable output. The device input is compatible with TTL−type input thresholds and the output has a full 5 V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic−level translator from 3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V CMOS Logic while operating at the high voltage power supply. The MC74VHC1GT00 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the MC74VHC1GT00 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage − input/output voltage mismatch, battery backup, hot insertion, etc. Features • High Speed: tPD = 3.1 ns (Typ) at VCC = 5 V • Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C • TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2 V • CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load • Power Down Protection Provided on Inputs and Outputs • Balanced Propagation Delays • Pin and Function Compatible with Other Standard Logic Families • Chip Complexity: FETs = 64 • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable • These Devices are Pb−Free and are RoHS Compliant VCC IN B IN A OUT Y GND IN A OUT Y & IN B Figure 1. Pinout Figure 2. Logic Symbol 1 2 3 4 5 PIN ASSIGNMENT 1 2 3 GND IN B IN A 4 5VCC OUT Y L L H H L H L H FUNCTION TABLE Inputs Output AB H H H L Y See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. ORDERING INFORMATION MARKING DIAGRAMS TSOP−5 / SOT23−5 / SC59−5 DT SUFFIX CASE 483 1 5 SC−88A / SC70−5 / SOT−353 DF SUFFIX CASE 419A 1 5 http://onsemi.com 1 5 VH M G G VH = Device Code M = Date Code* G = Pb−Free Package (Note: Microdot may be in either location) *Date Code orientation and/or position may vary depending upon manufacturing location. 1 5 VH M G G |
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