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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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UC1825A-SP Fiches technique(PDF) 6 Page - Texas Instruments |
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UC1825A-SP Fiches technique(HTML) 6 Page - Texas Instruments |
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6 / 40 page  6 UC1825A-SP SLUS873C – JANUARY 2009 – REVISED DECEMBER 2016 www.ti.com Product Folder Links: UC1825A-SP Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated (1) Parameters ensured by design and/or characterization, if not production tested. 7.5 Electrical Characteristics TA = –55°C to 125°C, RT = 3.65 kΩ, CT = 1 nF, VCC = 12 V, TA = TJ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFERENCE, VREF VO Ouput voltage TJ = 25°C, IO = 1 mA 5.05 5.1 5.15 V Line regulation 12 V ≤ VCC ≤ 20 V 2 15 mV Load regulation 1 mA ≤ IO ≤ 10 mA 5 20 mV Total output variation Line, load, temperature 5.03 5.17 V Temperature stability(1) T(min) < TA < T(max) 0.2 0.4 mV/°C Output noise voltage 10 Hz < f < 10 kHz 50 μVRMS Short circuit current VREF = 0 V 30 60 90 mA OSCILLATOR fOSC Initial accuracy(1) TJ = 25°C 375 400 425 kHz RT = 6.6 kΩ, CT = 220 pF, TA = 25°C 0.9 1 1.1 MHz Total variation(1) Line, temperature 350 450 kHz RT = 6.6 kΩ, CT = 220 pF 0.82 1.18 MHz Voltage stability 12 V < VCC < 20 V 1% Temperature stability T(min) < TA < T(max) ±5% High-level output voltage, clock 3.7 4 V Low-level output voltage, clock 0 0.2 V Ramp peak 2.6 2.8 3 V Ramp valley 0.7 1 1.25 V Ramp valley-to-peak 1.55 1.8 2 V IOSC Oscillator discharge current RT = OPEN, VCT = 2 V 8.5 10 11 mA ERROR AMPLIFIER Input offset voltage 2 10 mV Input bias current 0.6 3 μA Input offset current 0.1 1 μA Open loop gain 1 V < VO < 4 V 60 95 dB CMRR Common mode rejection ratio 1.5 V < VCM < 5.5 V 75 95 dB PSRR Power supply rejection ratio 12 V < VCC < 20 V 85 110 dB IO(sink) Output sink current VEAOUT = 1 V 1 2.5 mA IO(src) Output source current VEAOUT = 4 V –0.5 –1.3 mA High-level output voltage IEAOUT = –0.5 mA 4.5 4.7 5 V Low-level output voltage IEAOUT = –1 mA 0 0.5 1 V Gain bandwidth product(1) f = 200 kHz 6 12 MHz Slew rate(1) 5 7 V/μs PWM COMPARATOR IBIAS Bias current, RAMP VRAMP = 0 V –1 –8 μA Minimum duty cycle 0% Maximum duty cycle 85% tLEB Leading edge blanking time RLEB = 2 kΩ, CLEB = 470 pF 300 375 450 ns RLEB Leading edge blanking resistance VCLK/LEB = 3 V 8.5 10 11.5 k Ω VZDC Zero DC threshold voltage, EAOUT VRAMP = 0 V 1.10 1.25 1.4 V tDELAY Delay-to-output time(1) VEAOUT = 5-V to 0-V step 50 120 ns |
Numéro de pièce similaire - UC1825A-SP_16 |
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Description similaire - UC1825A-SP_16 |
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