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STGAP1AS Fiches technique(PDF) 9 Page - STMicroelectronics |
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STGAP1AS Fiches technique(HTML) 9 Page - STMicroelectronics |
9 / 70 page DocID029344 Rev 2 9/70 STGAP1AS Pin connection 70 2 Pin connection Figure 2. Pin connection (top view) Table 1. Pin description Pin no. Pin name Type Function 7 VDD Power supply Power supply for low voltage section and internal 3.3 V regulator 6 VREG Power supply Internal 3.3 V regulator output and supply pin 11 SD Logic input Shutdown input (active low) 9 IN+ Logic input Gate command input 8 IN-/DIAG2 Logic input/open drain output Gate command input /open drain diagnostic output 10 DIAG1 Open drain output Open drain diagnostic output 1, 12 GND Ground Low voltage section ground 4CS Logic input SPI chip select (active low) 5 CK Logic input SPI clock 3 SDI Logic input SPI serial data input 2 SDO Logic output SPI serial data output 19 VCECLAMP Analog input VCE active clamping protection 18 DESAT Analog input/output Desaturation protection 15 VREGISO Power supply Internal regulator output pin for decoupling 17 VH Power supply Positive power supply for high voltage section 20 GON Analog output Gate source output SDI SDO GND 1 3 2 CLAMP VL ASC 24 23 22 21 CK DESAT VCECLAMP GON 20 19 17 18 5 7 6 8 VH IN+ 16 9 15 10 14 11 13 12 GOFF 4 VDD GND VREG VL VREGISO SENSE GNDISO DIAG1 IN-/DIAG2 CS SD |
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