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BM92A50MWV Fiches technique(PDF) 5 Page - Rohm |
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BM92A50MWV Fiches technique(HTML) 5 Page - Rohm |
5 / 35 page 5/31 TSZ02201-0232AA000470-1-2 © 2016 ROHM Co., Ltd. All rights reserved. 21.Sep.2016 Rev.001 www.rohm.com TSZ22111 • 15 • 001 BM92A50MWV 2. Pin Description Table 2-1 Pin Description PKG PIN# Pin Name BLOCK I/O Type Digital I/O Level Description 1 GND GND I GND Ground 2 VSTR/ATST2 TEST/Debug IO Analog Analog TEST/ Debug Pin2 3 IDSEL/ATST1 TEST/Debug I Analog VCCIN SMBus ID (device address) selection “H”:1Ah, “L”:18h /Debug Pin1 4 XRST Interface I Digital VCCIN Digital block Reset 5 VCCIN USB-PD O Analog Internal Power supply (For internal use, need to connect capacitor to GND 6 VSVR POWER I Power 5V SVR INPUT and SPDSRC_FET_SRC voltage 7 DSCHG Interface IO Analog Discharge NMOS Drain 8 GND GND I GND Ground 9 VB POWER I Power Power Source from VBUS 10 GPIO4 Interface I Digital Mode fixation (Fix: L) 11 GPIO5 (D0) Interface O Digital VCCIN D0 signal 12 GPIO6 (D1) Interface O Digital VCCIN D1 signal 13 GPIO7 (D2) Interface O Digital VCCIN D2 signal 14 DBGRSTCK TEST IO Digital VDDIO Test for logic 15 DBGMODDT TEST IO Digital VDDIO Test for logic 16 GPIO0 (VOUT_EN) Interface I Digital VDDIO VOUT_EN signal 17 GPIO1 (ALERT#) Interface O (Note 1) Digital VDDIO Alert signal 18 VDDIO POWER I Power Interface Voltage 19 SMDATA Interface IO Digital VDDIO SMBus Data 20 SMCLK Interface I Digital VDDIO SMBus Clock 21 S2_DRV_G1 FET Gate Control O Analog Power Path FET Gate Control SPDSNK_G1 22 S2_DRV_SRC FET Gate Control I Analog Power Path FET BG/SRC Voltage SPDSNK_SRC 23 S2_DRV_G2 FET Gate Control O Analog Power Path FET Gate Control SPDSNK_G2 24 S1_DRV_G1 FET Gate Control O Analog Power Path FET Gate Control SPDSRC_G1 25 S1_DRV_SRC FET Gate Control I Analog Power Path FET BG/SRC Voltage SPDSRC_SRC 26 S1_DRV_G2 FET Gate Control O Analog Power Path FET Gate Control SPDSRC_G2 (Note 1) N-ch Open Drain |
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