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MC14526BDWG Fiches technique(PDF) 1 Page - ON Semiconductor

No de pièce MC14526BDWG
Description  Presettable 4-Bit Down Counters
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Fabricant  ONSEMI [ON Semiconductor]
Site Internet  http://www.onsemi.com
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© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 8
1
Publication Order Number:
MC14526B/D
MC14526B
Presettable 4-Bit Down
Counters
The MC14526B binary counter is constructed with MOS P−channel
and N−channel enhancement mode devices in a monolithic structure.
This device is presettable, cascadable, synchronous down counter
with a decoded “0” state output for divide−by−N applications. In
single stage applications the “0” output is applied to the Preset Enable
input. The Cascade Feedback input allows cascade divide−by−N
operation with no additional gates required. The Inhibit input allows
disabling of the pulse counting function. Inhibit may also be used as
a negative edge clock.
This complementary MOS counter can be used in frequency
synthesizers, phase−locked loops, and other frequency division
applications requiring low power dissipation and/or high noise
immunity.
Features
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Edge−Clocked Design: Incremented on Positive Transition of
Clock or Negative Transition of Inhibit
Asynchronous Preset Enable
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
DC Supply Voltage Range
VDD
− 0.5 to +18.0
V
Input or Output Voltage Range
(DC or Transient)
Vin,
Vout
−0.5 to VDD + 0.5
V
Input or Output Current
(DC or Transient) per Pin
Iin, Iout
±10
mA
Power Dissipation per Package (Note 1)
PD
500
mW
Operating Temperature Range
TA
− 55 to +125
°C
Storage Temperature Range
Tstg
− 65 to +150
°C
Lead Temperature
(8−Second Soldering)
TL
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Package: –7.0 mW/
_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
SOIC−16 WB
DW SUFFIX
CASE 751G
MARKING DIAGRAM
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G
= Pb−Free Package
1
1
14526B
AWLYWWG


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