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9ZXL1550 Fiches technique(PDF) 7 Page - Integrated Device Technology |
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9ZXL1550 Fiches technique(HTML) 7 Page - Integrated Device Technology |
7 / 18 page REVISION E 11/20/15 7 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 9ZXL1550 DATASHEET Electrical Characteristics–DIF LP-HCSL Differential Outputs Electrical Characteristics–Current Consumption TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Slew rate Trf Scope averaging on 1.5 2.7 4 V/ns 1, 2, 3 Slew rate matching ∆Trf Slew rate matching. 8.8 20 % 1, 2, 4 Voltage High VHigh 660 787 850 Voltage Low VLow -150 33 150 Max Voltage Vmax 845 1150 Min Voltage Vmin -300 9 Crossing Voltage (abs) Vcross_abs Scope averaging off 250 471 550 mV 1, 5 Crossing Voltage (var) ∆-Vcross Scope averaging off 14 140 mV 1, 6 2 Measured from differential waveform 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is to limit Vcross induced modulation by setting ∆-Vcross to be smaller than Vcross absolute. mV Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) Single ended signal using absolute value. Includes 300mV of over/undershoot. (Scope mV 1Guaranteed by design and characterization, not 100% tested in production. C L = 2pF with RS = 27Ω for Zo = 85Ω differential trace impedance. 3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES IDDVDD All outputs 100MHz, CL = 2pF; Zo = 85Ω 17 30 mA 1 IDDVDDA/R All outputs 100MHz, CL = 2pF; Zo = 85Ω 15 20 mA 1 IDDVDDIO All outputs 100MHz, CL = 2pF; Zo = 85Ω 112 150 mA 1 IDDVDDPD All differential pairs low-low 2.1 4 mA 1 IDDVDDA/RPD All differential pairs low-low 4.4 7 mA 1 IDDVDDIOPD All differential pairs low-low 0.0 1.5 mA 1 1Guaranteed by design and characterization, not 100% tested in production. Operating Supply Current Powerdown Current |
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