LM2685 datasheet(7/9 Pages) NSC

No de pièce	LM2685

Description	Dual Output Regulated Switched Capacitor Voltage Converter

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Fabricant	NSC [National Semiconductor (TI)]

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Detailed Device Description

(Continued)

is added is determined by the parasitic resistance (R

ds(on) of

the MOSFET switches and the ESR of the capacitors) and

the charge transfer loss between capacitors.

Shutdown and Load Disconnect

In addition to the nominal charge pump and regulator func-

tions, the LM2685 features shutdown and load disconnect

circuitry. CE (chip enable) and SDP (shutdown positive) per-

form the same task with opposite input polarities. When CE

is low or SDP is high, all circuit blocks are disabled and V

05

falls to ground potential. This is the same result as when the

die temperature exceeds 150˚C (typical), and the device’s

internal thermal shutdown is triggered.

Forcing SDN (shutdown negative) high disables only the in-

verting charge pump. The doubling charge pump and the

LDO regulator continue to operate, so the V

05 and the VPSW

remain at 5V.

The LM2685 incorporates two low impedance switches tied

to the V

05 and VNEG outputs, because some special applica-

tions require load disconnect and this is achievable via the

switches. Switch PSW connects V

05 to VPSW, and switch

NSW connects V

NEG to VNSW. In normal operation, these

switches are closed, allowing 5V loads to be tied to either

V

05 or VPSW and −5V loads to be tied to either VNEG or

V

NSW. Driving SDN high opens switch NSW only, while forc-

ing CE low or SDP high, opens both the PSW and NSW.

Application Information

Capacitor Selection

The output resistance and ripple voltage are dependent on

the capacitance and ESR values of the external capacitors.

Voltage Doubler External Capacitors

The selection of capacitors are based on the specifications

of the dropout voltage (which equals I

OUT ROUT), the output

voltage ripple, and the converter efficiency.

where R

SW is the sum of the ON resistance of the internal

MOSFET switches as shown in

Figure 2.

The peak-to-peak output voltage ripple is determined by the

oscillator frequency, the capacitance and ESR of the capaci-

tor C3.

High capacitance (2.2µF to higher), low ESR capacitors can

reduce the output resistance and the voltage ripple.

where I

Q(V+) is the quiescent power loss of the IC device,

and I

2

LR is the conversion loss associated with the switch

on-resistance, the two external capacitors and their ESRs.

Low ESR capacitors (table to be referenced) are recom-

mended to maximize efficiency, reduce the output voltage

drop and voltage ripple.

+5 LDO Regulator External Capacitors

The voltage doubler output capacitor, C3, serves as the input

capacitor of the +5 LDO regulator. The output capacitor C4,

must meet the requirement for minimum amount of capaci-

tance and appropriate ESR (Equivalent Serving Resistance)

for proper operation. The ESR value must remain within the

regions of stability as shown in

Figure 4, Figure 5 and Figure

6 to ensure output’s stability. A minimum capacitance of 1µF

is required at the output. This can be increased without limit,

but a 4.7µF tantalum capacitor is recommended for loads

ranging upto the maximum specification. With lighter loads

of less or equal to 10mA, ceramic capacitor of at least 1µF

and ESR in the milliohms can be used. This has to be con-

nected to V

PSW pin instead of the V05 pin.

Any output capacitor used should have a good tolerance

over temperature for capacitance and ESR values. The

larger the capacitor, with ESR within the stable region, the

better the stability and noise performance.

DS101100-5

FIGURE 3. Voltage Inverter Principle

DS101100-25

FIGURE 4. ESR Curve for C

OUT = 2.2µF

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