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8V79S680NLGI8 Fiches technique(PDF) 11 Page - Integrated Device Technology |
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8V79S680NLGI8 Fiches technique(HTML) 11 Page - Integrated Device Technology |
11 / 52 page 11 ©2016 Integrated Device Technology, Inc August 4, 2016 8V79S680 Datasheet Table 8: Individual Clock Output (QCLK_y) Settingsa PD STYLE EN A[1:0] Output Power Terminationb State Amplitude (mV) 1 X X XOff 100 differential (LVDS) or no termination Off X 0 0 0 XX On 100 differential (LVDS) Disablec X 1 00 Enable 250 01 500 10 750 11 1000 1 0 XX 50 to VT (LVPECL) Disable X 1 00 Enable 250 01 500 10 750 11 1000 a. Applicable to clock outputs: QCLK_y and QREF_r outputs in clock mode (MUX_r = 0). b. See Section “Application Information” on page 42 for output termination information. c. Differential output is disabled in static low state: QCLK_y = L, nQCLK_y = H. Table 9: Individual SYSREF Output (QREF_r) Settingsa PD STYLE Enable A[1:0] nBIAS Output Power Terminationb State Amplitude (mV) 1 X X X XOff 100 differential or no termination Off X 0 0 0 XX 0 On 100 differential (LVDS) Disablec X 1 00 0 Enabled 250 01 0 See Table 10 500 1 Enabled 10 0750 11 01000 1 0 XX 050 to VT (LVPECL) Disable X 1 00 Enable 250 01 500 10 750 11 1000 a. Applicable QREF_r outputs when configured as SYSREF output (MUX_r = 1). b. See Section “Application Information” on page 42 for output termination information. c. Differential output is disabled in static low state: QCLK_y = L, nQCLK_y = H. |
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