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LM2631 Fiches technique(PDF) 4 Page - National Semiconductor (TI) |
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LM2631 Fiches technique(HTML) 4 Page - National Semiconductor (TI) |
4 / 12 page Electrical Characteristics (Continued) Specifications in standard type face are for T j = 25˚C and those with boldface type apply over full operating junction tem- perature range. V IN =10V, GND = PGND = 0V,unless otherwise stated. (Notes 5, 6) Symbol Parameter Conditions Typical Limit Units Voltage Reference V REF Reference Voltage (Line Regulation) 4.5V < V IN < 30V 1.238 V 1.219/1.219 V(min) 1.251/1.262 V(max) Reference Voltage (Load Regulation) 0µA < I REF < 50 µA 1.238 V 1.219/1.219 V(min) 1.251/1.262 V(max) Logic Inputs and Outputs V IH Minimum High Level Input Voltage (SD, FPWM and SYNC) 2.4 V(min) V IL Maximum Low Level Input Voltage (FPWM and SYNC) 0.8 V(max) Maximum Low Level Input Voltage (SD) 0.5 V(max) Maximum Input Leakage Curren1t (SD , FPWM and SYNC) Logic Input Voltage 0V or 5V ±0.1 µA V OH PGOOD High Level Output Voltage PGOOD Sourcing 50 µA 2.7 V 2.4 V(min) V OL PGOOD Low Level Output Voltage PGOOD Sinking 50 µA 0 V 0.5 V(max) Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Electrical specifications do not apply when operating the device outside of its rated operating conditions. Note 2: The maximum allowable power dissipation is calculated by using PDmax = (TJmax -TA)/θJA , where TJmax is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance of the specified package. The 720 mW rating results from using 160˚C, 70˚C, and 125˚C/W for TJmax,TA, and θJA respectively. A θJA of 125˚C/W represents the worst-case condition of no heat sinking of the 20-pin TSSOP. Heat sinking allows the safe dissipation of more power. The Absolute Maximum power dissipation must be derated by 8 mW per ˚C above 70˚C ambient. The LM263 actively limits its junction temperature to about 160˚C. Note 3: For detailed information on soldering plastic small-outline packages, refer to the Packaging Databook available from National Semiconductor Corporation. Note 4: For testing purposes, ESD was applied using the human-body model, a 100 pF capacitor discharged through a 1.5 k Ω resistor. Note 5: A typical is the center of characterization data taken with TA = TJ = 25˚C. Typicals are not guaranteed. Note 6: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production with TA = TJ = 25˚C. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Note 7: This limit is guaranteed by design. Note 8: Percentage limits are determined by measuring the shutdown latch threshold at the FB pin, and dividing it by the nominal reference voltage. Note 9: Pulling 2.94 µA out of FADJ pin simulates adjusting the oscillator frequency with a 350 k Ω resistor connected from FADJ to GND. Typical Performance Characteristics Efficiency vs Load Current (FPWM = Low, V OUT = 3.3V) DS100937-11 Efficiency (FPWM = High, Input Voltage = 16V V OUT= 2.9V) DS100937-12 www.national.com 4 |
Numéro de pièce similaire - LM2631 |
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Description similaire - LM2631 |
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