Moteur de recherche de fiches techniques de composants électroniques
  French  ▼
ALLDATASHEET.FR

X  

CAT24C64WI-GT3 Fiches technique(PDF) 4 Page - ON Semiconductor

No de pièce CAT24C64WI-GT3
Description  64 Kb I2C CMOS Serial EEPROM
Download  16 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricant  ONSEMI [ON Semiconductor]
Site Internet  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CAT24C64WI-GT3 Fiches technique(HTML) 4 Page - ON Semiconductor

  CAT24C64WI-GT3 Datasheet HTML 1Page - ON Semiconductor CAT24C64WI-GT3 Datasheet HTML 2Page - ON Semiconductor CAT24C64WI-GT3 Datasheet HTML 3Page - ON Semiconductor CAT24C64WI-GT3 Datasheet HTML 4Page - ON Semiconductor CAT24C64WI-GT3 Datasheet HTML 5Page - ON Semiconductor CAT24C64WI-GT3 Datasheet HTML 6Page - ON Semiconductor CAT24C64WI-GT3 Datasheet HTML 7Page - ON Semiconductor CAT24C64WI-GT3 Datasheet HTML 8Page - ON Semiconductor CAT24C64WI-GT3 Datasheet HTML 9Page - ON Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 16 page
background image
CAT24C64
www.onsemi.com
4
Power−On Reset (POR)
Each CAT24C64 incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state. The device will power up into Standby
mode after VCC exceeds the POR trigger level and will
power down into Reset mode when VCC drops below the
POR trigger level. This bi−directional POR behavior
protects the device against ‘brown−out’ failure following a
temporary loss of power.
Pin Description
SCL: The Serial Clock input pin accepts the clock signal
generated by the Master.
SDA: The Serial Data I/O pin accepts input data and delivers
output data. In transmit mode, this pin is open drain. Data is
acquired on the positive edge, and is delivered on the
negative edge of SCL.
A0, A1 and A2: The Address inputs set the device address
that must be matched by the corresponding Slave address
bits. The Address inputs are hard−wired HIGH or LOW
allowing for up to eight devices to be used (cascaded) on the
same bus. When left floating, these pins are pulled LOW
internally. The Address inputs are not available for use with
WLCSP 4−bumps.
WP: When pulled HIGH, the Write Protect input pin
inhibits all write operations. When left floating, this pin is
pulled LOW internally. The WP input is not available for the
WLCSP 4−bumps, therefore all write operations are allowed
for the device in this package.
Functional Description
The CAT24C64 supports the Inter−Integrated Circuit
(I2C) Bus protocol. The protocol relies on the use of a Master
device, which provides the clock and directs bus traffic, and
Slave devices which execute requests. The CAT24C64
operates as a Slave device. Both Master and Slave can
transmit or receive, but only the Master can assign those
roles.
I2C Bus Protocol
The 2−wire I2C bus consists of two lines, SCL and SDA,
connected to the VCC supply via pull−up resistors. The
Master provides the clock to the SCL line, and either the
Master or the Slaves drive the SDA line. A ‘0’ is transmitted
by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data
transfer may be initiated only when the bus is not busy (see
A.C. Characteristics). During data transfer, SDA must
remain stable while SCL is HIGH.
START/STOP Condition
An SDA transition while SCL is HIGH creates a START
or STOP condition (Figure 2). The START consists of a
HIGH to LOW SDA transition, while SCL is HIGH. Absent
the START, a Slave will not respond to the Master. The
STOP completes all commands, and consists of a LOW to
HIGH SDA transition, while SCL is HIGH.
Device Addressing
The Master addresses a Slave by creating a START
condition and then broadcasting an 8−bit Slave address. For
the CAT24C64, the first four bits of the Slave address are set
to 1010 (Ah); the next three bits, A2, A1 and A0, must match
the logic state of the similarly named input pins. The devices
in WLCSP 4−bumps respond only to the Slave Address with
A2 A1 A0 = 000 (CAT24C64C4CTR) or to A2 A1 A0 = 100
(CAT24C64AC4CTR). The R/W bit tells the Slave whether
the Master intends to read (1) or write (0) data (Figure 3).
Acknowledge
During the 9th clock cycle following every byte sent to the
bus, the transmitter releases the SDA line, allowing the
receiver to respond. The receiver then either acknowledges
(ACK) by pulling SDA LOW, or does not acknowledge
(NoACK) by letting SDA stay HIGH (Figure 4). Bus timing
is illustrated in Figure 5.
START
CONDITION
STOP
CONDITION
SDA
SCL
Figure 2. Start/Stop Timing
Figure 3. Slave Address Bits
10
1
0
DEVICE ADDRESS*
A2
A1
A0
R/W
* The devices in WLCSP 4−bumps respond only to the Slave Address with: A2 A1 A0 = 000, CAT24C64C4CTR
* The devices in WLCSP 4−bumps respond only to the Slave Address with: A2 A1 A0 = 100, CAT24C64AC4CTR


Numéro de pièce similaire - CAT24C64WI-GT3

FabricantNo de pièceFiches techniqueDescription
logo
Catalyst Semiconductor
CAT24C64WI-GT3 CATALYST-CAT24C64WI-GT3 Datasheet
552Kb / 18P
   64-Kb I2C CMOS Serial EEPROM
logo
ON Semiconductor
CAT24C64WI-GT3 ONSEMI-CAT24C64WI-GT3 Datasheet
190Kb / 15P
   64 kb I2C CMOS Serial EEPROM
July, 2010 ??Rev. 14
CAT24C64WI-GT3 ONSEMI-CAT24C64WI-GT3 Datasheet
185Kb / 15P
   64 kb I2C CMOS Serial EEPROM
August, 2013 ??Rev. 17
CAT24C64WI-GT3 ONSEMI-CAT24C64WI-GT3 Datasheet
185Kb / 15P
   64 kb I2C CMOS Serial EEPROM
August, 2013 ??Rev. 17
CAT24C64WI-GT3 ONSEMI-CAT24C64WI-GT3 Datasheet
123Kb / 13P
   64 Kb I2C CMOS Serial EEPROM
April, 2018 ??Rev. 27
More results

Description similaire - CAT24C64WI-GT3

FabricantNo de pièceFiches techniqueDescription
logo
ON Semiconductor
CAT24C64LI ONSEMI-CAT24C64LI Datasheet
185Kb / 15P
   64 kb I2C CMOS Serial EEPROM
August, 2013 ??Rev. 17
logo
Catalyst Semiconductor
CAT24C64 CATALYST-CAT24C64 Datasheet
552Kb / 18P
   64-Kb I2C CMOS Serial EEPROM
logo
ON Semiconductor
LE2464DXA ONSEMI-LE2464DXA Datasheet
305Kb / 17P
   64 kb I2C CMOS Serial EEPROM
August 2016 - Rev. 1
LE2464RDXA ONSEMI-LE2464RDXA Datasheet
353Kb / 17P
   64 kb I2C CMOS Serial EEPROM
August 2016 - Rev. 1
CAV24C64 ONSEMI-CAV24C64_16 Datasheet
106Kb / 11P
   64-Kb I2C CMOS Serial EEPROM
February, 2016 ??Rev. 2
CAT24C64LI-G ONSEMI-CAT24C64LI-G Datasheet
185Kb / 15P
   64 kb I2C CMOS Serial EEPROM
August, 2013 ??Rev. 17
CAT24C64 ONSEMI-CAT24C64 Datasheet
190Kb / 15P
   64 kb I2C CMOS Serial EEPROM
July, 2010 ??Rev. 14
CAV24C64 ONSEMI-CAV24C64 Datasheet
143Kb / 10P
   64-Kb I2C CMOS Serial EEPROM
March, 2011 ??Rev. 0
N24S64B ONSEMI-N24S64B Datasheet
104Kb / 11P
   64 Kb I2C CMOS Serial EEPROM
August, 2018 ??Rev. 0
CAT24C64 ONSEMI-CAT24C64_18 Datasheet
123Kb / 13P
   64 Kb I2C CMOS Serial EEPROM
April, 2018 ??Rev. 27
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16


Fiches technique Télécharger

Go To PDF Page


Lien URL




Politique de confidentialité
ALLDATASHEET.FR
ALLDATASHEET vous a-t-il été utile ?  [ DONATE ] 

À propos de Alldatasheet   |   Publicité   |   Contactez-nous   |   Politique de confidentialité   |   Echange de liens   |   Fabricants
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com