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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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S29GL512T10FHAyyx Fiches technique(PDF) 60 Page - Cypress Semiconductor |
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S29GL512T10FHAyyx Fiches technique(HTML) 60 Page - Cypress Semiconductor |
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60 / 105 page  Document Number: 002-00247 Rev. *G Page 60 of 105 S29GL01GT, S29GL512T Hardware Interface 8. Signal Descriptions 8.1 Address and Data Configuration Address and data are connected in parallel (ADP) via separate signal inputs and I/Os. 8.2 Input/Output Summary Table 8.1 I/O Summary Symbol Type Description RESET# Input Hardware Reset. At VIL, causes the device to reset control logic to its standby state, ready for reading array data. CE# Input Chip Enable. At VIL, selects the device for data transfer with the host memory controller. OE# Input Output Enable. At VIL, causes outputs to be actively driven. At VIH, causes outputs to be high impedance (High-Z). WE# Input Write Enable. At VIL, indicates data transfer from host to device. At VIH, indicates data transfer is from device to host. Amax-A0 Input Address inputs. A25-A0 for S29GL01GT A24-A0 for S29GL512T DQ14-DQ0 Input/Output Data inputs and outputs DQ15/A-1 Input/Output DQ15: Data inputs and outputs A-1: LSB address input in byte mode WP#/ACC Input Write Protect. At VIL, disables program and erase functions in the lowest or highest address 64-kword (128-kB) sector of the device. At VIH, the sector is not protected. At VHH, automatically places device in unlock bypass mode. WP# has an internal pull up; When unconnected WP# is at VIH. RY/BY# Output – open drain Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At VIL, the device is actively engaged in an Embedded Algorithm such as erasing or programming. At High-Z, the device is ready for read or a new command write - requires external pull-up resistor to detect the High-Z state. Multiple devices may have their RY/BY# outputs tied together to detect when all devices are ready. BYTE# Input Selects data bus width. At VIL, the device is in byte configuration and data I/O pins DQ7-DQ0 are active and DQ15/A-1 becomes the LSB address input. At VIH, the device is in word configuration and data I/O pins DQ15-DQ0 are active. VCC Power Supply Core power supply VIO Power Supply Versatile I/O power supply. VSS Power Supply Power supplies ground NC No Connect Not Connected internally. The pin/ball location may be used in Printed Circuit Board (PCB) as part of a routing channel. RFU No Connect Reserved for Future Use. Not currently connected internally but the pin/ball location should be left unconnected and unused by PCB routing channel for future compatibility. The pin/ball may be used by a signal in the future. DNU Reserved Do Not Use. Reserved for use by Cypress. The pin/ball is connected internally. The input has an internal pull down resistance to VSS. The pin/ball can be left open or tied to VSS on the PCB. |
Numéro de pièce similaire - S29GL512T10FHAyyx |
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Description similaire - S29GL512T10FHAyyx |
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