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S29GL01GT12TFByyx Datasheet(Fiches technique) 27 Page - Cypress Semiconductor

Numéro de pièce S29GL01GT12TFByyx
Description  1 Gbit (128 Mbyte), 512 Mbit (64 Mbyte)
Télécharger  105 Pages
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Fabricant  CYPRESS [Cypress Semiconductor]
Site Internet  http://www.cypress.com
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 27 page
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Document Number: 002-00247 Rev. *G
Page 27 of 105
S29GL01GT, S29GL512T
The system must write the Program Resume command to exit the Program Suspend mode and continue the programming
operation. Further writes of the Program Resume command are ignored. Another Program Suspend command can be written after
the device has resumed programming.
Program operations can be interrupted as often as necessary but in order for a program operation to progress to completion there
must be some periods of time between resume and the next suspend command greater than or equal to tPRS in Embedded
Algorithm Controller (EAC) on page 19.
Program suspend and resume is not supported while entered in an ASO.
5.4.3
Accelerated Programming
The device supports program operations when the system asserts VHH on the WP#/ACC or ACC pin. When WP#/ACC or ACC pin is
lowered back to VIH or VIL the device exits the Accelerated Programming mode and returns to normal operation. The WP#/ACC is
VHH tolerant but is not designed to accelerate the program functions. If the system asserts VHH on this input, the device
automatically enters the Unlock Bypass mode. The system can then use the Write Buffer Load command sequence provided by the
Unlock Bypass mode. Note that if a ‘Write-to-Buffer-Abort Reset’ is required while in Unlock Bypass mode, the full 3-cycle RESET
command sequence must be used to reset the device. Removing VHH from the ACC input, upon completion of the embedded
program operation, returns the device to normal operation. Note that the WP#/ACC pin must not be at VHH for operations other than
accelerated programming, or device damage may result. WP# contains an internal pull-up; when unconnected, WP# is at VIH.
Accelerated programming is supported at room temperature only.
Sectors must be unlocked prior to raising WP#/ACC to VHH.
It is recommended that WP#/ACC apply VHH after power-up sequence is completed. In addition, it is recommended that WP#/
ACC apply from VHH to VIH/VIL before powering down VCC/VIO.
5.4.4
Unlock Bypass
This device features an Unlock Bypass mode to facilitate shorter programming commands. Once the device enters the Unlock
Bypass mode, only two write cycles are required to program data, instead of the normal four cycles.The device will also support the
Write to Buffer command and will only require four+ write cycles.
This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total
programming time. The Command Summary on page 48 shows the requirements for the unlock bypass command sequences.
During the unlock bypass mode, only the Read, Program, Write Buffer Programming, Write-to-Buffer-Abort Reset, Status Register
Read, Status Register Clear, Soft Reset, Unlock Bypass Sector Erase, Unlock Bypass Chip Erase, Unlock Erase Suspend/Resume,
Unlock Bypass Suspend/Resume, and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must
issue the two-cycle unlock bypass reset command sequence. The first cycle address is ‘don't care’ and the data 90h. The second
cycle need only contain the data 00h. The sector then returns to the read mode.
Software Functions and Sample Code
The following are C source code examples of using the unlock bypass entry, program, and exit functions. Refer to the Cypress Low
Level Driver User’s Guide for general information on Cypress flash memory software development guidelines.
Table 5.2 Unlock Bypass Entry (LLD Function = lld_UnlockBypassEntryCmd)
Cycle
Description
Operation
Byte Address
Word Adddress
Data
1
Unlock
Write
Base + AAAh
Base + 555h
00AAh
2
Unlock
Write
Base + 555h
Base + 2AAh
0055h
3
Entry Command
Write
Base + AAAh
Base + 555h
0020h




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