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S29GL512T11DHIyyx Fiches technique(PDF) 79 Page - Cypress Semiconductor |
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S29GL512T11DHIyyx Fiches technique(HTML) 79 Page - Cypress Semiconductor |
79 / 105 page Document Number: 002-00247 Rev. *G Page 79 of 105 S29GL01GT, S29GL512T Note: 1. Not 100% tested. Table 11.7 Read Operation VIO = VCC = 2.7 V to 3.6 V (–40 °C to +125 °C) Parameter Description Test Setup Speed Option Unit JEDEC Std 120 tAVAV tRC Read Cycle Time (Note 1) CE# = VIL OE# = VIL 512 Mb, 1 Gb Min 120 ns tAVQV tACC Address to Output Delay OE# = VIL 512 Mb, 1 Gb Max 120 ns tELQV tCE Chip Enable to Output Delay 512 Mb, 1 Gb Max 120 ns tPACC Page Access Time 512 Mb, 1 Gb Max 15 ns tGLQV tOE Output Enable to Output Delay Read Max 25 ns Poll Max 35 ns tAXQX tOH Output Hold time from Addresses, CE# or OE#, whichever occurs first Min 0 ns tEHQZ tDF Chip Enable or Output Enable to Output High-Z (Note 1) Max 15 ns tOEH Output Enable Hold Time (Note 1) Read Min 0 ns Poll Min 10 ns tASO Address Setup Time Poll Min 15 ns tASH Address Hold Time Poll Min 0 ns tCEPH CE# High Poll Min 20 ns tOEP OE# Low Poll Min 25 ns tOEPH OE# High Poll Min 20 ns tOEC OE# Cycle Time Poll Min 60 ns tASSB Automatic Sleep to Standby time (Note 1) CE# = VIL, Address stable Typ 5 μs Max 8 μs tBLEL tFLEL BYTE# Low to CE# Low Min 10 ns tBHEL tFHEL BYTE# High to CE# Low Min 10 ns tBLQV tFLQV BYTE# Low to Output High-Z (Note 1) Max 1 μs tBHQV tFHQV BYTE# High to Output Delay Max 1 μs |
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