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S29GL01GT13TFNyyxx Datasheet(Fiches technique) 54 Page - Cypress Semiconductor

Numéro de pièce S29GL01GT13TFNyyxx
Description  1 Gbit (128 Mbyte), 512 Mbit (64 Mbyte)
Télécharger  105 Pages
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Fabricant  CYPRESS [Cypress Semiconductor]
Site Internet  http://www.cypress.com
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Document Number: 002-00247 Rev. *G
Page 54 of 105
S29GL01GT, S29GL512T
3. Except for the following, all bus cycles are write cycle: read cycle during Read, ID/CFI Read (Manufacturing ID / Device ID), Indicator Bits,
Secure Silicon Region Read, SSR Lock Read, and 2nd cycle of Status Register Read .
4. Address bits Amax-A11 are don't cares for unlock and command cycles, unless SA or PA required. (Amax is the Highest Address pin.).
5. No unlock or command cycles required when reading array data.
6. The Reset command is required to return to reading array data when device is in the ASO mode, or if DQ5 goes High (while the device is
providing status data).
7. Command is valid when device is ready to read array data.
8. The Unlock-Bypass command is required prior to the Unlock-Bypass-Program command and the unlock bypass write to buffer commands.
9. The Unlock-Bypass-Reset command is required to return to reading array data when the device is in the unlock bypass mode.
10. The system can read and program/program suspend in non-erasing sectors, or enter the ID-CFI ASO, when in the Erase Suspend mode. The
Erase Suspend command is valid only during a sector erase operation.
11. The Erase Resume/Program Resume command is valid only during the Erase Suspend/Program Suspend modes.
12. Issue this command sequence to return to Read State after detecting device is in a Write-to-Buffer-Abort state. IMPORTANT: the full command
sequence is required if resetting out of ABORT.
13. The Exit command returns the device to reading the array.
14. The password portion can be entered or read in any order as long as the entire 64-bit password is entered or read. Addresses are
20h-27h if the SSR3 is being accessed.
15. For PWDx, only one portion of the password can be programmed per each A0 command. Portions of the password must be programmed in
sequential order (PWD0 - PWD7).
16. All Lock Register bits are one-time programmable. The program state = 0 and the erase state = 1. Also, both the Persistent Protection Mode
Lock Bit and the Password Protection Mode Lock Bit cannot be programmed at the same time or the Lock Register Bits Program operation
aborts and returns the device to Read State. Lock Register bits that are reserved for future use are undefined and may be 0’s or 1's.
17. If any of the Entry commands was issued, an Exit command must be issued to reset the device into Read State.
18. Protected State = 00h, Unprotected State = 01h. The sector address for DYB set, DYB clear, or PPB Program command may be any location
within the sector - the lower order bits of the sector address are don't care.
19. See Section 5.4.7.2, Sector Erase on page 30 for description of Multi-Sector Erase.
20. In x8 mode the WC represents 2 x8 WBL/PD cycles (e.g. if WC = 0, then 5th bus cycle would load data to lower byte address A-1 = low and 6th
bus cycle would load data to upper byte address A-1 = high).




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