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S29GL01GT13TFNyyxx Datasheet(Fiches technique) 36 Page - Cypress Semiconductor

Numéro de pièce S29GL01GT13TFNyyxx
Description  1 Gbit (128 Mbyte), 512 Mbit (64 Mbyte)
Télécharger  105 Pages
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Fabricant  CYPRESS [Cypress Semiconductor]
Site Internet  http://www.cypress.com
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Document Number: 002-00247 Rev. *G
Page 36 of 105
S29GL01GT, S29GL512T
5.5
Status Monitoring
There are three methods for monitoring EA status. Previous generations of the S29GL flash family used the methods called Data
Polling and Ready/Busy# (RY/BY#) Signal. These methods are still supported by the S29GL-T family. One additional method is
reading the Status Register.
5.5.1
Status Register
The status of program and erase operations is provided by a single 16-bit status register. The Status Register Read command is
written followed by a read access of the status register information. When the Status Register read command is issued, the current
status is captured (by the rising edge of WE#) into the register and the ASO is entered. The contents of the status register is aliased
(overlaid) the full memory address space. Valid read (CE# and OE# low) access in the Status Register ASO exits the ASO (with the
rising edge of CE# or OE# for tCEPH/tOEPH time) and returns to the address space map in use when the Status Register Read
command was issued. While in x8 mode the full Status Register can be read (both the upper byte and lower byte) with one Status
Register entry by keeping CE# and OE# low and having a transition on A-1. Write operations are ignored and the device will stay in
Status Register ASO.The status register contains bits related to the results – success or failure – of the most recently completed
Embedded Algorithms (EA):
Erase Status (bit 5),
Program Status (bit 4),
Write Buffer Abort (bit 3),
Sector Locked Status (bit 1),
Continuity Check Pattern Detected (bit 0).
and, bits related to the current state of any in process EA:
Device Busy (bit 7),
Erase Suspended (bit 6),
Program Suspended (bit 2),
The current state bits indicate whether an EA is in process, suspended, or completed.
The upper 8 bits (bits 15:8) are reserved. These have undefined High or Low value that can change from one status read to another.
These bits should be treated as don't care and ignored by any software reading status.
The Soft Reset Command will clear to 0 bits [5, 4, 1, 0] of the status register if Status Register bit 3 =0. It will not affect the current
state bits.
The Clear Status Register Command will clear to 0 bits [5, 4, 3, 1, 0] of the status register but will not affect the current state bits.




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