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S29GL01GT11FHVyyx Fiches technique(PDF) 82 Page - Cypress Semiconductor |
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S29GL01GT11FHVyyx Fiches technique(HTML) 82 Page - Cypress Semiconductor |
82 / 105 page Document Number: 002-00247 Rev. *G Page 82 of 105 S29GL01GT, S29GL512T 11.4.2 Asynchronous Write Operations Note: 1. Not 100% tested. Figure 11.8 Back to Back Write Operation Timing Diagram Note: 1. Address are Amax:A0 in word mode; Amax:A-1 in byte mode, Data are DQ15-DQ0 in word mode; DQ7-DQ0 in byte mode. Table 11.9 Write Operations Parameter Description VIO = 2.7V to VCC VIO = 1.65V to VCC Unit JEDEC Std tAVAV tWC Write Cycle Time (Note 1) Min 60 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# Low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 45 ns tAHT Address Hold Time From CE# or OE# High during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 30 ns tWHDX tDH Data Hold Time Min 0 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP WE# Pulse Width Min 25 ns tWHWL tWPH WE# Pulse Width High Min 20 ns tSEA Sector Erase Time-Out Min 50 µs Amax-A0 CE# OE# WE# DQ15-DQ0 tDS tDH tWP tAS tAH tWPH tWC tCS tCH |
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