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S29GL01GT11FHVyyx Fiches technique(PDF) 61 Page - Cypress Semiconductor |
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S29GL01GT11FHVyyx Fiches technique(HTML) 61 Page - Cypress Semiconductor |
61 / 105 page Document Number: 002-00247 Rev. *G Page 61 of 105 S29GL01GT, S29GL512T 8.3 Word/Byte Configuration The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ0-DQ15 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. The BYTE# pin can only be switch while the device is in standby (read mode). The BYTE# pin has an internal pull-up. Though not required in a x16 only system, the pin should be connected to high (e.g. VIO) 8.4 Versatile I/O Feature The maximum output voltage level driven by, and input levels acceptable to, the device are determined by the VIO power supply. This supply allows the device to drive and receive signals to and from other devices on the same bus having interface signal levels different from the device core voltage. 8.5 Ready/Busy# (RY/BY#) RY/BY# is a dedicated, open drain output pin that indicates whether an Embedded Algorithm, Power-On Reset (POR), or Hardware Reset is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in a command sequence, when VCC is above VCC minimum during POR, or after the falling edge of RESET#. Since RY/BY# is an open drain output, several RY/BY# pins can be tied together in parallel with a pull up resistor to VIO. If the output is Low (Busy), the device is actively erasing, programming, or resetting. (This includes programming in the Erase Suspend mode). If the output is High (Ready), the device is ready to read data (including during the Erase Suspend mode), or is in the standby mode. Table 5.6, Data Polling Status on page 40 shows the outputs for RY/BY# in each operation. If an Embedded algorithm has failed (Program / Erase failure as result of max pulses or Program Abort), RY/BY# will stay Low (busy) until status register bits 4 and 5 are cleared and the reset command is issued. If an Embedded algorithm has failed (Sector is locked), RY/BY# will return High (ready). This includes Erase or Programming on a locked sector. 8.6 Hardware Reset The RESET# input provides a hardware method of resetting the device to standby state. When RESET# is driven Low for at least a period of tRP, the device immediately: terminates any operation in progress, exits any ASO, tristates all outputs, resets the Status Register, resets the EAC to standby state. CE# is ignored for the duration of the reset operation (tRPH). To meet the Reset current specification (ICC5) CE# must be held High. To ensure data integrity any operation that was interrupted should be reinitiated once the device is ready to accept another command sequence. |
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