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S29GL01GT11TFIyyx Fiches technique(PDF) 29 Page - Cypress Semiconductor |
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S29GL01GT11TFIyyx Fiches technique(HTML) 29 Page - Cypress Semiconductor |
29 / 105 page Document Number: 002-00247 Rev. *G Page 29 of 105 S29GL01GT, S29GL512T 5.4.6 Blank Check The Blank Check command will confirm if the selected main flash array sector is currently erased (i.e. “Trust Worthy” and “Blank”). The Blank Check command does not allow for reads to the array during the Blank Check. Reads to the array while this command is executing will return polling data. To initiate a Blank Check on a Sector, write 33h to address 555h in the Sector, while the EAC is in the standby state. The Blank Check command may not be written while the device is actively programming or erasing or suspended. Use the Status Register or Polling method (equivalent to an embedded erase operation) to determine if the device is busy or completed. Once completed the Status Register and the Polling method will display if the sector is blank (equivalent to a successful erase operation) or if the sector is not erased. Bit 5 of the Status Register (SR[5]) will be cleared to 0 if the sector is blank. If the sector is not blank than SR[5] will be set to 1, RD/BY# will stay low, and either a Software Reset / ASO Exit command or a Status Register Clear command is required to return the device to the Standby State. As soon as any bit is found to not be erased, the device will halt the operation and report the results. Once the Blank Check is completed, the EAC will return to the Standby State. 5.4.7 Erase Methods 5.4.7.1 Chip Erase The chip erase function erases the entire main Flash Memory Array. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all 0 data pattern prior to electrical erase. After a successful chip erase, all locations within the device contain FFFFh. The system is not required to provide any controls or timings during these operations. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. When WE# goes high, at the end of the 6th cycle, the RY/BY# goes low. When the Embedded Erase algorithm is complete, the EAC returns to the standby state. Note that while the Embedded Erase operation is in progress, the system can not read data from the device. The system can determine the status of the erase operation by reading the RY/BY#, Status Register or using Data Polling. Refer to Ready/Busy# (RY/BY#) on page 61 for information on RY/ BY#. Refer to Status Register on page 36 for information on these status bits. Refer to Data Polling Status on page 37 for more information. Once the chip erase operation has begun, only a Status Read, Hardware RESET or Power cycle are valid. All other commands are ignored. However, a Hardware Reset or Power Cycle immediately terminates the erase operation and returns to read mode after tRPH time. If a chip erase operation is terminated, the chip erase command sequence must be reinitiated once the device has returned to the idle state to ensure data integrity. See Table 5.7 on page 44, Asynchronous Write Operations on page 82 and Alternate CE# Controlled Write Operations on page 88 for parameters and timing diagrams. Sectors protected by the ASP DYB and PPB bits will not be erased. See ASP on page 13. If a sector is protected during chip erase, chip erase will skip the protected sector and continue with next sector erase. The status register erase status bit and sector lock bit are not set to 1 by a failed erase on a protected sector. |
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