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S29GL01GT11FAIyyx Datasheet(Fiches technique) 42 Page - Cypress Semiconductor

Numéro de pièce S29GL01GT11FAIyyx
Description  1 Gbit (128 Mbyte), 512 Mbit (64 Mbyte)
Télécharger  105 Pages
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Fabricant  CYPRESS [Cypress Semiconductor]
Site Internet  http://www.cypress.com
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Document Number: 002-00247 Rev. *G
Page 42 of 105
S29GL01GT, S29GL512T
During embedded algorithm error status the Status Register will show the following:
SR[7] = 1; Valid status displayed
SR[6] = X; May or may not be erase suspended during the EA error
SR[5] = 1 on erase or blank check error; else = 0
SR[4] = 1 on program or password unlock error; else = 0
SR[3] = 0; Write buffer abort
SR[2] = 0; Program suspended
SR[1] = 0; Protected sector
SR[0] = X; RFU, treat as don’t care (masked)
When the embedded algorithm error status is detected, it is necessary to clear the error status in order to return to normal operation,
with RY/BY# High, ready for a new read or command write. The error status can be cleared by writing:
Reset command
Status Register Clear command
Commands that are accepted during embedded algorithm error status are:
Status Register Read
Reset command
Status Register Clear command
5.6.2
Protection Error
If an embedded algorithm attempts to change data within a protected area (program, or erase of a protected sector or OTP area) the
device (EAC) goes busy for a period of tDP then returns to normal operation. During the busy period the RY/BY# output remains
Low, data polling status continues to be overlaid on all address locations, and the status register shows not ready with invalid status
bits (SR[7] = 0).
During the protection error status busy period the data polling status will show the following:
DQ7 is the inversion of the DQ7 bit in the last word loaded into the write buffer. DQ7 = 0 for an erase failure
DQ6 continues to toggle, independent of the address used to read status
DQ5 = 0; to indicate no failure of the embedded operation during the busy period
DQ4 is RFU and should be treated as don’t care (masked)
DQ3 = 1 to indicate embedded sector erase in progress
DQ2 continues to toggle, independent of the address used to read status
DQ1 = 0; Write buffer abort error
DQ0 is RFU and should be treated as don’t care (masked)
Commands that are accepted during the protection error status busy period are:
Status Register Read
When the busy period ends the device returns to normal operation, the data polling status is no longer overlaid, RY/BY# is High, and
the status register shows ready with valid status bits. The device is ready for flash array read or write of a new command.
After the protection error status busy period the Status Register will show the following:
SR[7] = 1; Valid status displayed
SR[6] = X; May or may not be erase suspended after the protection error busy period
SR[5] = 1 on erase error, else = 0
SR[4] = 1 on program error, else = 0




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