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S29GL01GT11FAIyyx Fiches technique(PDF) 38 Page - Cypress Semiconductor

No de pièce S29GL01GT11FAIyyx
Description  1 Gbit (128 Mbyte), 512 Mbit (64 Mbyte)
Download  105 Pages
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Fabricant  CYPRESS [Cypress Semiconductor]
Site Internet  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

S29GL01GT11FAIyyx Fiches technique(HTML) 38 Page - Cypress Semiconductor

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Document Number: 002-00247 Rev. *G
Page 38 of 105
S29GL01GT, S29GL512T
After an erase command sequence is written, if the sector selected for erasing is protected, Data# Polling on DQ7 is active for tDP,
then the device returns to reading array data.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ6-DQ0 while
Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7.
Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the
program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be still invalid. Valid data on DQ7-D00
appears on successive read cycles.
When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ15-DQ0 (Dq7-DQ0 in x8
mode) on the following read cycles. This is because DQ7 may change asynchronously with DQ6-DQ0 while Output Enable (OE#) is
asserted Low. This is illustrated in Figure 11.17 on page 87. Table 5.6 on page 40 shows the outputs for Data# polling on DQ7.
Figure 5.2 on page 24 shows the Data# polling algorithm use in Write Buffer Programming.
Valid DQ7 data polling status may only be read from:
the address of the last word loaded into the Write Buffer for a Write Buffer programming operation;
the location of a single word programming operation;
a location in a sector being erased, or evaluate erase status, or blank checked;
or a location in any sector during chip erase.
Figure 5.5 Data# Polling Algorithm
Note:
1. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.
5.5.2.2
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device
has entered the Program Suspend or Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising
edge of the final WE# pulse in the command sequence (prior to the program or erase operation).
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The
system may use either OE# or CE# to control the read cycles). When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if the sector selected for erasing is protected, DQ6 toggles for tDP, then the EAC
returns to standby (Read Mode). If the selected sector is not protected, the Embedded Erase algorithm erases the unprotected
sector.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or erase-suspended. When the device
is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Program
START
Read DQ7-DQ0
-
FAIL
DQ7 = Data?
No
Yes
DQ5 = 1?
No
Yes
DQ7 = Data?
No
Yes
PASS
Read DQ 7 -DQ0


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