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S26KL128S Fiches technique(PDF) 11 Page - Cypress Semiconductor

No de pièce S26KL128S
Description  512 Mbit (64 Mbyte), 256 Mbit (32 Mbyte), 128 Mbit (16 Mbyte) 1.8V/3.0V
Download  98 Pages
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Fabricant  CYPRESS [Cypress Semiconductor]
Site Internet  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

S26KL128S Fiches technique(HTML) 11 Page - Cypress Semiconductor

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S26KL512S / S26KS512S
S26KL256S / S26KS256S
S26KL128S / S26KS128S
Document Number: 001-99198 Rev. *F
Page 11 of 98
4.
HyperBus Protocol
All bus transactions can be classified as either read or write. A bus transaction is started with CS# going Low with CK = Low and
CK# = High. The transaction to be performed is presented to the HyperFlash device during the first three clock cycles in a DDR
manner using all six clock edges. These first three clocks transfer three words of Command / Address (CA0, CA1, CA2) information
to define the transaction characteristics:
 Read or write transaction.
 Whether the transaction will be to the memory array or to register space.
– Although the HyperBus protocol provides for slave devices that have both memory and register address spaces, HyperFlash
memories described in this specification do not differentiate between memory and registers as separate address spaces.
There is a single address space selected by any transaction, independent of whether the transaction indicates the target
location is in memory space or register space. Write transactions always place the transaction address and data into a a
command register set (buffer). Read transactions return data from the memory array or from a register address space window
that has been temporarily overlaid within the single address space by the execution of commands. The single address space
with register space overlays methodology is backward compatible with legacy parallel NOR Flash memory program and erase
software drivers.
 Whether a transaction will use a linear or wrapped burst sequence.
– HyperFlash write transactions do not support burst sequence and ignore the burst type indication. Write command
transactions transfer a single word per write. Only the Word Program command write data transfer may be done with a linear
burst at up to 50 MHz.
 The target half-page address (row and upper order column address).
 The target Word (within half-page) address (lower order column address).
Once the transaction has been defined, a number of idle clock cycles are used to satisfy any read latency requirements before data
is transferred. Once the target data has been transferred the HyperBus master host completes the transaction by driving CS# High
with CK = Low and CK# = High. Data is transferred as 16-bit values with the first eight bits (15-8) transferred on a High going CK
(write data or CA bits) or RWDS edge (read data) and the second eight bits (7-0) being transferred on the Low going CK or RWDS
edge. Data transfers during read or write operations can be ended at any time by bringing CS# High when CK = Low and
CK# = High. Read data is edge aligned with RWDS transitions and Write data is center aligned with clock edges.


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