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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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S26KL128S Fiches technique(PDF) 10 Page - Cypress Semiconductor |
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S26KL128S Fiches technique(HTML) 10 Page - Cypress Semiconductor |
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10 / 98 page  S26KL512S / S26KS512S S26KL256S / S26KS256S S26KL128S / S26KS128S Document Number: 001-99198 Rev. *F Page 10 of 98 3. Signal Description Figure 5. HyperFlash Interface Note: 1. M = Mandatory; O = Optional; P/G = Power / Ground Table 2. Signal Descriptions Symbol Type M / O Description CS# Input M Chip Select. HyperFlash bus transactions are initiated with a High to Low transition. HyperFlash bus transactions are terminated with a Low to High transition. CK, CK# Input M Differential Clock. Command / Address / Data information is input or output with respect to the crossing of the CK and CK# signals. CK# is only used on the 1.8V devices and may be left open or connected to CK on 3V devices. RWDS Output M Read Write Data Strobe. Output data during read transactions are edge aligned with RWDS. DQ[7..0] Input / Output M Data Input / Output. Command / Address / Data information is transferred on these DQs during read and write transactions. PSC, PSC# Input O Phase Shifted Clock. PSC/PSC# allows independent skewing of the RWDS signal with respect to the CK/CK# inputs. PSC# is only used on the 1.8V device. PSC and PSC# may be driven High and Low respectively or both may be driven Low during write transactions. INT# Output (open drain) O INT Output. When Low, the device is indicating that an internal event has occurred. This signal is intended to be used as a system level interrupt for the device to indicate that an on-chip event has occurred. INT# is an open-drain output. RESET# Input O Hardware Reset. When Low, the device will self initialize and return to the array read state. RWDS and DQ[7:0] are placed into the High-Z state when RESET# is Low. RESET# includes a weak pull-up, if RESET# is left unconnected it will be pulled up to the High state. RSTO# Output (open drain) O RSTO# Output. RSTO# is an open-drain output used to indicate when a POR is occurring within the device and can be used as a system level reset signal. Upon completion of the internal POR the RSTO# signal will transition from Low to high impedance after a user defined timeout period has elapsed. Upon transition to the high impedance state the external pull-up resistance will pull RSTO# High and the device immediately is placed into the Standby state. VCC Power Supply P/G Core Power. VCCQ Power Supply P/G Input / Output Power. VSS Power Supply P/G Core Ground. VSSQ Power Supply P/G Input / Output Ground. CS# CK# CK PSC DQ[7:0] RWDS PSC# VSS VSSQ VCC VCCQ RESET# INT# RSTO# |
Numéro de pièce similaire - S26KL128S |
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Description similaire - S26KL128S |
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