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CY8C4247BZI-L479 Fiches technique(PDF) 4 Page - Cypress Semiconductor

No de pièce CY8C4247BZI-L479
Description  Programmable System-on-Chip
Download  46 Pages
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Fabricant  CYPRESS [Cypress Semiconductor]
Site Internet  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C4247BZI-L479 Fiches technique(HTML) 4 Page - Cypress Semiconductor

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PSoC® 4: PSoC 4200-L Family
Datasheet
Document Number: 001-91686 Rev. *E
Page 4 of 46
Figure 2. Block Diagram
PSoC 4200-L Block Diagram
The PSoC 4200-L devices include extensive support for
programming, testing, debugging, and tracing both hardware
and firmware.
The ARM Serial_Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator Integrated Development Environment (IDE)
provides fully integrated programming and debug support for
PSoC 4200-L devices. The SWD interface is fully compatible
with industry-standard third-party tools. The PSoC 4200-L family
provides a level of security not possible with multi-chip appli-
cation solutions or with microcontrollers. This is due to its ability
to disable debug features, robust flash protection, and because
it allows customer-proprietary functionality to be implemented in
on-chip programmable blocks.
The debug circuits are enabled by default and can only be
disabled in firmware. If not enabled, the only way to re-enable
them is to erase the entire device, clear flash protection, and
reprogram the device with new firmware that enables debugging.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. Because all programming, debug, and test inter-
faces are disabled when maximum device security is enabled,
PSoC 4200-L with device security enabled may not be returned
for failure analysis. This is a trade-off the PSoC 4200-L allows
the customer to make.
PSoC4A-L
M0S8 Architecture
32-bit
AHB-Lite
Deep Sleep
Hibernate
Active/Sleep
CPU Subsystem
SRAM
32 KB
SRAM Controller
ROM
8 KB
ROM Controller
FLASH
256 KB
Read Accelerator
SPCIF
SWD/TC
NVIC, IRQMX
Cortex
M0
48 MHz
FAST MUL
System Interconnect (Multi Layer AHB)
DataWire/
DMA
Initiator/MMIO
I/O Subsystem
80x GPIO, 14x GPIO_OVT, 2x SIO
Peripherals
System Resources
Power
Clock
WDT
ILO
Reset
Clock Control
DFT Logic
Test
IMO
DFT Analog
Sleep Control
PWRSYS
REF
POR
LVD
NVLatches
BOD
WIC
Reset Control
XRES
Peripheral Interconnect (MMIO)
PCLK
Port Interface & Digital System Interconnect (DSI)
512B
Power Modes
SMX
SAR ADC
(12-bit)
x1
Programmable
Analog
CTBm
x2
2x OpAmp
2x PLL
ECO
Programmable
Digital
x8
...
UDB
UDB
High Speed I /O Matrix, 1x Programmable I /O


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