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CY8C4247LTI-L475 Fiches technique(PDF) 9 Page - Cypress Semiconductor

No de pièce CY8C4247LTI-L475
Description  Programmable System-on-Chip
Download  46 Pages
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Fabricant  CYPRESS [Cypress Semiconductor]
Site Internet  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C4247LTI-L475 Fiches technique(HTML) 9 Page - Cypress Semiconductor

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PSoC® 4: PSoC 4200-L Family
Datasheet
Document Number: 001-91686 Rev. *E
Page 9 of 46
CAN Blocks
There are two independent CAN 2.0B blocks, which are certified
CAN conformant.
GPIO
The PSoC 4200-L has 96 GPIOs. The GPIO block implements
the following:
Eight drive strength modes including strong push-pull, resistive
pull-up and pull-down, weak (resistive) pull-up and pull-down,
open drain and open source, input only, and disabled
Input threshold select (CMOS or LVTTL)
Individual control of input and output disables
Hold mode for latching previous state (used for retaining I/O
state in Deep Sleep mode and Hibernate modes)
Selectable slew rates for dV/dt related noise control to improve
EMI
The pins are organized in logical entities called ports, which are
8-bit in width. During power-on and reset, the blocks are forced
to the disable state so as not to crowbar any inputs and/or cause
excess turn-on current. A multiplexing network known as a
high-speed I/O matrix is used to multiplex between various
signals that may connect to an I/O pin. Pin locations for
fixed-function peripherals are also fixed to reduce internal multi-
plexing complexity (these signals do not go through the DSI
network). DSI signals are not affected by this and any pin may
be routed to any UDB through the DSI network.
Data output and pin state registers store, respectively, the values
to be driven on the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled and each
I/O port has an interrupt request (IRQ) and interrupt service
routine (ISR) vector associated with it (13 for PSoC 4200-L).
There are 14 GPIO pins that are overvoltage tolerant (VIN can
exceed VDD). The overvoltage cells will not sink more than 10 µA
when their inputs exceed VDDIO in compliance with I2C specifi-
cations. Meeting the I2C minimum fall time requirement for FM
and FM+ may require the slower slew rate setting depending on
bus loading (also applies to all GPIO and SIO pins).
SIO
The Special I/O (SIO) pins have the following features in addition
to the GPIO features:
Overvoltage protection and hot swap capability
Programmable switching thresholds
Programmable output pull-up voltage capability
They allow interfacing to buses, such as I2C with full I2C compat-
ibility and interfacing to devices operating at different voltage
levels. There are two SIO pins on the PSoC4200-L.
Special Function Peripherals
LCD Segment Drive
The PSoC 4200-L has an LCD controller, which can drive up to
eight commons and up to 56 segments. Any pin can be either a
common or a segment pin. It uses full digital methods to drive the
LCD segments requiring no generation of internal LCD voltages.
The two methods used are referred to as digital correlation and
PWM.
Digital correlation pertains to modulating the frequency and
levels of the common and segment signals to generate the
highest RMS voltage across a segment to light it up or to keep
the RMS signal zero. This method is good for STN displays but
may result in reduced contrast with TN (cheaper) displays.
PWM pertains to driving the panel with PWM signals to effec-
tively use the capacitance of the panel to provide the integration
of the modulated pulse-width to generate the desired LCD
voltage. This method results in higher power consumption but
can result in better results when driving TN displays. LCD
operation is supported during Deep Sleep refreshing a small
display buffer (4 bits; 1 32-bit register per port).
CapSense
CapSense is supported on all pins in the PSoC 4200-L through
two CapSense Sigma-Delta (CSD) blocks that can be connected
to any pin through an analog mux bus that any GPIO pin can be
connected to via an Analog switch. CapSense function can thus
be provided on any pin or group of pins in a system under
software control. A component is provided for the CapSense
block to make it easy for the user.
Shield voltage can be driven on another Mux Bus to provide
water tolerance capability. Water tolerance is provided by driving
the shield electrode in phase with the sense electrode to keep
the shield capacitance from attenuating the sensed input.
Each CapSense block has two IDACs which can be used for
general purposes if CapSense is not being used.(both IDACs are
available in that case) or if CapSense is used without water
tolerance (one IDAC is available). The two CapSense blocks can
be used independently.


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