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MB95F816KPMC-G-SNE2 Fiches technique(PDF) 85 Page - Cypress Semiconductor |
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MB95F816KPMC-G-SNE2 Fiches technique(HTML) 85 Page - Cypress Semiconductor |
85 / 121 page MB95810K Series Document Number: 002-04694 Rev. *A Page 85 of 121 (VCC = 2.88 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C) *: The external clock signal is input to X0 and the inverted external clock signal to X1. Parameter Symbol Pin name Condition Value Unit Remarks Min Typ Max Clock cycle time tHCYL X0, X1 61.5 1000 ns When the main oscillation circuit is used X0 X1: open 83.4 1000 ns When an external clock is used X0, X1 * 30.8 1000 ns tLCYL X0A, X1A 30.5 µs When the subclock is used Input clock pulse width tWH1, tWL1 X0 X1: open 33.4 ns When an external clock is used, the duty ratio should range between 40% and 60%. X0, X1 * 12.4 ns tWH2, tWL2 X0A —15.2 µs Input clock rising time and falling time tCR, tCF X0, X0A X1: open — 5ns When an external clock is used X0, X1, X0A, X1A *— — 5 ns CR oscillation start time tCRHWK —— — — 50 µs When the main CR clock is used tCRLWK —— — — 30 µs When the sub-CR clock is used PLL oscillation start time tMCRPLLWK —— — — 100 µs When the main CR PLL clock is used X0, X1 0.8 VCC 0.2 VCC 0.2 VCC 0.8 VCC tWH1 tWL1 0.2 VCC tHCYL tCR tCF • Input waveform generated when an external clock (main clock) is used When a crystal oscillator or a ceramic oscillator is used When an external clock is used X0 X1 X0 X1 FCH FCH When an external clock is used (X1 is open) X0 X1 Open FCH • Figure of main clock input port external connection |
Numéro de pièce similaire - MB95F816KPMC-G-SNE2 |
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Description similaire - MB95F816KPMC-G-SNE2 |
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