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CYW20733A3KFB1G Fiches technique(PDF) 44 Page - Cypress Semiconductor |
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CYW20733A3KFB1G Fiches technique(HTML) 44 Page - Cypress Semiconductor |
44 / 67 page Document No. 002-14859 Rev. *R Page 44 of 67 CYW20733 ■ PCM Electrical Timing Slave—Long Frame Sync ■ PCM Electrical Timing Master—Long Frame Sync ■ PCM Electrical Timing Burst (Slave Rx Only)—Long Frame Sync Note: The TX and RX timings are combined on the same diagram. The CYW20733 can only either transmit or receive in a given slot. PCM Electrical Timing Slave — Short Frame Sync Figure 18. PCM Electrical Timing Slave—Short Frame Sync Diagram Table 31. PCM Electrical Timing Slave—Short Frame Sync Characteristics Reference Characteristics Minimum Typical Maximum Unit 1 PCM bit clock frequency – – 12 MHz 2 PCM bit clock low time 41 – – ns 3 PCM bit clock high time 41 – – ns 4 PCM_SYNC setup time 8 – – ns 5 PCM_SYNC hold time 8 – – ns 6 PCM_OUT delay 0 – 25 ns 7 PCM_IN setup 8 – – ns 8 PCM_IN hold 8 – – ns 9 Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance 0 – 25 ns PCM_BCLK PCM_SYNC PCM_OUT 1 2 3 4 5 6 PCM_IN 7 9 High impedance 8 Bit 15 (Previous Frame) Bit 15 (Previous Frame) Bit 0 Bit 0 |
Numéro de pièce similaire - CYW20733A3KFB1G |
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Description similaire - CYW20733A3KFB1G |
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